-
1.发明授权公开(公告)号：US11410730B2
公开(公告)日：2022-08-09
申请号：US17096055
申请日：2020-11-12
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Ramin Ghodsi
Abstract: Memory including an array of memory cells might include an input buffer having calibration circuitry, a first input, a second input, and an output; and calibration logic having an input selectively connected to the output of the input buffer and comprising an output connected to the calibration circuitry, wherein the calibration logic is configured to cause the memory to determine whether the input buffer exhibits offset while a particular voltage level is applied to the first and second inputs of the input buffer, and, in response to determining that the selected input buffer exhibits offset, apply an adjustment to the calibration circuitry while the particular voltage level is applied to the first and second inputs until a logic level of the output of the selected input buffer transitions.
-
公开(公告)号：US20210304829A1
公开(公告)日：2021-09-30
申请号：US17344141
申请日：2021-06-10
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tommaso Vali , Ramin Ghodsi
Abstract: Memories might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to determine a particular voltage level applied to each of the access lines that is deemed to activate each memory cell of a first subset of the strings of series-connected memory cells programmed to store respective data states that are each lower than or equal to a first data state of a plurality of data states, apply the particular voltage level to a particular access line of the plurality of access lines, and for each memory cell connected to the particular access line that is contained in a second subset of the strings of series-connected memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.
-
公开(公告)号：US11107536B2
公开(公告)日：2021-08-31
申请号：US16916216
申请日：2020-06-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tommaso Vali , Luca De Santis , Ramin Ghodsi
Abstract: Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.
-
公开(公告)号：US20210065825A1
公开(公告)日：2021-03-04
申请号：US17095291
申请日：2020-11-11
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tommaso Vali , Ramin Ghodsi
Abstract: Memory might include a plurality of strings of memory cells, a plurality of access lines each connected to the strings of memory cells, and a controller configured to cause the memory to increase a voltage level applied to each of the access lines, determine a particular voltage level at which each memory cell of a first set of strings of memory cells is deemed to be activated while increasing the voltage level applied to the access lines, decrease the voltage level applied to a particular access line without decreasing the voltage level applied to each remaining access line, and, for each memory cell connected to the particular access line and contained in a second set of strings of memory cells, determine whether that memory cell is deemed to be activated while applying the particular voltage level to the particular access line.
-
公开(公告)号：US20200335171A1
公开(公告)日：2020-10-22
申请号：US16916216
申请日：2020-06-30
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Tommaso Vali , Luca De Santis , Ramin Ghodsi
Abstract: Memory having a controller configured to cause the memory to determine a plurality of activation voltage levels for the plurality of memory cells, determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels with each of the activation voltage level distributions corresponding to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, and assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage of that memory cell and the determined plurality of transition voltage levels.
-
Patent Agency Ranking
公开(公告)号：US10381080B2
公开(公告)日：2019-08-13
申请号：US15280301
申请日：2016-09-29
Applicant: Micron Technology, Inc.
Inventor： Feng Pan , Jaekwan Park , Ramin Ghodsi
Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.
-
公开(公告)号：US20190214089A1
公开(公告)日：2019-07-11
申请号：US16178989
申请日：2018-11-02
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Qiang Tang , Ramin Ghodsi
IPC: G11C16/10 , H03K19/0185 , G11C16/26 , G11C16/04 , H03K19/00
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/26 , H03K19/0005 , H03K19/018528
Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.
-
公开(公告)号：US20190074070A1
公开(公告)日：2019-03-07
申请号：US16182355
申请日：2018-11-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Feng Pan , Ramin Ghodsi , Qiang Tang
Abstract: Apparatuses and methods for reducing read disturb are described herein. An example apparatus may include a first memory subblock including a first select gate drain (SGD) switch and a first select gate source (SGS) switch, a second memory subblock including a second SGD switch and a second SGS switch, and an access line associated with the first and second memory subblocks. The apparatus may include a control unit configured to enable the first and second SGD switches and the first and second SGS switches during a first portion of a read operation and to provide a first voltage on the access line during the first portion. The control unit may be configured to disable the first SGD switch and the first SGS switches during a second portion of the read operation and to provide a second voltage on the access line during the second portion.
-
公开(公告)号：US10115465B2
公开(公告)日：2018-10-30
申请号：US15479520
申请日：2017-04-05
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Ramin Ghodsi
Abstract: Methods of operating a memory include receiving a plurality of digits of data, determining a value of the plurality of digits of data, and selecting a function to represent the value of the plurality of digits of data. The selected function is a function of a cell number of each memory cell within a grouping of memory cells. The methods further include determining a desired threshold voltage of a particular memory cell of the grouping of memory cells corresponding to the value of the selected function for the cell number of the particular memory cell, and programming the particular memory cell to its desired threshold voltage.
-
公开(公告)号：US10115457B2
公开(公告)日：2018-10-30
申请号：US15444982
申请日：2017-02-28
Applicant: Micron Technology, Inc.
Inventor： Qiang Tang , Feng Pan , Ramin Ghodsi , Mark A. Helm
Abstract: Apparatuses and methods for threshold voltage (Vt) distribution determination are described. A number of apparatuses can include sense circuitry configured to determine a first current on a source line of an array of memory cells, the first current corresponding to a first quantity of memory cells of a group of memory cells that conducts in response to a first sensing voltage applied to an access line and determine a second current on the source line, the second current corresponding to a second quantity of memory cells of the group that conducts in response to a second sensing voltage applied to the access line. The number of apparatuses can include a controller configured to determine at least a portion of a Vt distribution corresponding to the group of memory cells based, at least in part, on the first current and the second current.
-
-
-
-
-
-
-
-
-
Search Results
90
records
(took 0.03 seconds)
