公开(公告)号：US11545219B2

公开(公告)日：2023-01-03

申请号：US16975619

申请日：2020-03-24

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Efrem Bolandrina ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C7/00 ,  G11C16/04 ,  G11C16/32 ,  G11C16/26 ,  G11C16/10

Abstract: A memory device with single transistor drivers and methods to operate the memory device are described. In some embodiments, the memory device may comprise memory cells at cross points of access lines of a memory array, a first even single transistor driver configured to drive a first even access line to a discharging voltage during an IDLE phase, to drive the first even access line to a floating voltage during an ACTIVE phase, and to drive the first even access line to a read/program voltage during a PULSE phase, and a first odd single transistor driver configured to drive a first odd access line, the first odd access line physically adjacent to the first even access line, to the discharging voltage during the IDLE phase, to drive the first odd access line to the floating voltage during the ACTIVE phase, and to drive the first odd access line to a shielding voltage during the PULSE phase.

公开(公告)号：US11532345B2

公开(公告)日：2022-12-20

申请号：US17097749

申请日：2020-11-13

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto

IPC: G11C11/22 ,  G06F13/40 ,  G11C13/00

Abstract: Methods, systems, and apparatuses for self-referencing sensing schemes are described. A cell having two transistors, or other switching components, and one capacitor, such as a ferroelectric capacitor, may be sensed using a reference value that is specific to the cell. The cell may be read and sampled via one access line, and the cell may be used to generate a reference voltage and sampled via another access line. For instance, a first access line of a cell may be connected to one read voltage while a second access line of the cell is isolated from a voltage source; then the second access line may be connected to another read voltage while the first access line is isolate from a voltage source. The resulting voltages on the respective access lines may be compared to each other and a logic value of the cell determined from the comparison.

公开(公告)号：US20220321147A1

公开(公告)日：2022-10-06

申请号：US17222660

申请日：2021-04-05

Applicant: Micron Technology, Inc.

Inventor： Christophe Vincent Antoine Laurent ,  Riccardo Muzzetto

IPC: H03M13/29 ,  G06F11/10 ,  G11C15/04

Abstract: Methods, systems, and devices for fixed weight codewords for ternary memory cells are described. A memory device may generate a codeword from a set of data bits and invert a portion of the codeword so that the codeword is associated with a target distribution of programmable states. After inverting the portion of the codeword, the memory device store the codeword in a set of ternary cells according to a coding scheme. The memory device may read the codeword from the set of ternary cells and select one or more reference voltages for the set of ternary cells based on the target distribution for the codeword and the states of the ternary cells.

公开(公告)号：US11355174B2

公开(公告)日：2022-06-07

申请号：US16507419

申请日：2019-07-10

Applicant: Micron Technology, Inc.

Inventor： Riccardo Muzzetto

IPC: G11C11/22

Abstract: Self-referencing memory device, techniques, and methods are described herein. A self-referencing memory device may include a ferroelectric memory cell. The self-referencing memory device may be configured to determine a logic state stored in a memory cell based on a state signal generated using the ferroelectric memory cell and a reference signal generated using the ferroelectric memory cell. The biasing of the plate line of the ferroelectric memory cell may be used to generate the voltage need to generate the state signal during a first time period of an access operation and to generate the reference signal during a second time period of the access operation. Procedures and operations related to a self-referencing memory device are described.

公开(公告)号：US20220122659A1

公开(公告)日：2022-04-21

申请号：US17512586

申请日：2021-10-27

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C13/00

Abstract: The present disclosure relates to a method for reading memory cells, and may include applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, where the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, and detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, among other aspects. A related circuit, a related memory device and a related system are also disclosed.

公开(公告)号：US11289146B2

公开(公告)日：2022-03-29

申请号：US16552984

申请日：2019-08-27

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi ,  Riccardo Muzzetto

IPC: G11C11/22

Abstract: Methods, systems, and devices for word line timing management are described. In some examples, a digit line may be precharged as part of accessing a memory cell. The memory cell may include a storage component and a selection component. A word line may be coupled with the selection component, and the word line may be selected in order to couple the storage component with the digit line, by way of the selection component. The word line may be selected while the digit line is still being precharged, and the storage component may become coupled with the digit line with reduced delay after the end of precharging of the digit line, concurrent with the end of the precharging of the digit line, or while the digit line is still being charged. Related techniques for sensing a logic state stored by the memory cell are also described.

公开(公告)号：US20220068335A1

公开(公告)日：2022-03-03

申请号：US17498919

申请日：2021-10-12

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Riccardo Muzzetto ,  Umberto di Vincenzo

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C16/34

Abstract: A method for accessing of memory cells where a set of user data is stored in a plurality of memory cells of the memory array, including: latching a current row address of a selected plurality of memory access; comparing a last row address with the current row address; if the result of the comparison is negative, executing a leakage compensation algorithm through a memory sensing circuitry; if the result of the comparison is positive, waiting for the completion of a write to read procedure on the selected plurality of memory cells.

公开(公告)号：US11164626B2

公开(公告)日：2021-11-02

申请号：US16771657

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/00 ,  G11C13/00

Abstract: A method for reading memory cell, comprising the steps of applying a first read voltage to a plurality of memory cells, detecting first threshold voltages exhibited by the plurality of memory cells in response to application of the first read voltage, based on the first threshold voltages, associating a first logic state to one or more cells of the plurality of memory cells, applying a second read voltage to the plurality of memory cells, wherein the second read voltage has the same polarity of the first read voltage and a higher magnitude than an expected highest threshold voltage of memory cells in the first logic state, detecting second threshold voltages exhibited by the plurality of memory cells in response to application of the second read voltage, based on the second threshold voltages, associating a second logic state to one or more cells of the plurality of memory cells, applying a third read voltage to the plurality of memory cells, wherein the third read voltage has the same polarity of the first and second read voltages and is applied at least to a group of memory cells that, during the application the second read voltage, have been reprogrammed to an opposite logic state, detecting third threshold voltages exhibited by the plurality of memory cells in response to application of the third read voltage, and based on the third threshold voltages, associating one of the first or second logic state to one or more of the cells of the of the plurality of memory cells. A related circuit, a related memory device and a related system are also disclosed.

公开(公告)号：US10916288B1

公开(公告)日：2021-02-09

申请号：US16515666

申请日：2019-07-18

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Efrem Bolandrina ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C7/00 ,  G11C11/22

Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.

公开(公告)号：US20210020221A1

公开(公告)日：2021-01-21

申请号：US16515666

申请日：2019-07-18

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Efrem Bolandrina ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/22

Abstract: Methods, systems, and devices for sensing techniques for a memory cell are described to enable a latch to sense a logic state of a memory cell. A transistor coupled with a memory cell may boost a first voltage associated with the memory cell to a second voltage via one or more parasitic capacitances of the transistor. The second voltage may be developed on a first node of a sense component, and the second voltage may be shifted to a third voltage at a first node of the sense component by applying a voltage to a shift node coupled with a capacitor of the sense component. Similar boosting and shifting operations may be performed to develop a reference voltage on a second node of the sense component. The sense component may sense the state of the memory cell by comparing with the reference voltage.