公开(公告)号：US20240064328A1

公开(公告)日：2024-02-22

申请号：US18385044

申请日：2023-10-30

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/52 ,  H04N19/109 ,  H04N19/139 ,  H04N19/176 ,  H04N19/577

CPC classification number: H04N19/52 ,  H04N19/109 ,  H04N19/139 ,  H04N19/176 ,  H04N19/577

Abstract: An encoder: generates, in an inter prediction mode, a first prediction image of a current block to be processed, based on a derived motion vector; and generates a final prediction image of the current block by applying an update process to the first prediction image. Candidates for the update process include a first process and a second process. The first process is a BDOF process. The second process is a process of mixing the first prediction image with a second prediction image generated in intra prediction for the current block. In the applying of the update process, the first process and the second process are mutually exclusively applied.

公开(公告)号：US20240040158A1

公开(公告)日：2024-02-01

申请号：US18479663

申请日：2023-10-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Han Boon TEO ,  Chong Soon LIM ,  Hai Wei SUN ,  Che-Wei KUO ,  Chu Tong WANG ,  Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/82 ,  H04N19/107 ,  H04N19/176 ,  H04N19/186

CPC classification number: H04N19/82 ,  H04N19/107 ,  H04N19/176 ,  H04N19/186

Abstract: A decoder includes memory and a processor coupled to the memory and configured to: generate a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component; clip the first coefficient value such that the clipped first coefficient value is within a first range from −27 to 27−1; generate a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component; clip the second coefficient value such that the clipped second coefficient value is within a second range different from the first range; generate a third coefficient value by adding the clipped first coefficient value to the clipped second coefficient value; and generate a third reconstructed image sample of the chroma component using the third coefficient value.

公开(公告)号：US20230388536A1

公开(公告)日：2023-11-30

申请号：US18226952

申请日：2023-07-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/52 ,  H04N19/137 ,  H04N19/186

CPC classification number: H04N19/52 ,  H04N19/137 ,  H04N19/186 ,  H04N19/176

Abstract: An encoder includes circuitry and memory connected to the circuitry. In operation, the circuitry: derives an average value of motion vector values of two prediction candidates in a prediction candidate list for a merge mode, and registers the average value derived as new motion vector information of a new prediction candidate into the prediction candidate list; and derives new correction processing information regarding correction processing of a prediction image, and registers the new correction processing information derived into the prediction candidate list in association with the new motion vector information.

公开(公告)号：US20230362397A1

公开(公告)日：2023-11-09

申请号：US18355164

申请日：2023-07-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/44 ,  H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/513

CPC classification number: H04N19/44 ,  H04N19/105 ,  H04N19/139 ,  H04N19/176 ,  H04N19/521

Abstract: An image encoder includes circuitry and a memory, wherein the circuitry, in operation, determines whether inter prediction is to be applied to a current block; in response to determining that the inter prediction is to be applied to the current block, performs a partition prediction process; and, in response to determining that the inter prediction is not to be applied, encodes the current block without using the partition prediction process. The partition prediction process includes predicting first values of a set of pixels between a first partition and a second partition in the current block, using a first motion vector for the first partition; predicting second values of the set of pixels, using a second motion vector for the second partition; weighting the first values and the second values; and generating a prediction image for the current block using the weighted first values and the weighted second values.

公开(公告)号：US20230308692A1

公开(公告)日：2023-09-28

申请号：US18325906

申请日：2023-05-30

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/96 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176 ,  H04N19/18 ,  H04N19/66 ,  H04N19/91

CPC classification number: H04N19/96 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176 ,  H04N19/18 ,  H04N19/66 ,  H04N19/91

Abstract: An image encoder performs a first partitioning including using a first partition mode, without writing first splitting information indicative of the first partition mode into a bitstream, to split a first block into a plurality of second blocks in response to that the first block is located adjacent to an edge of a picture and that the dimensions of the first block satisfy a first condition; and performs a second partitioning on the second block by writing second splitting information indicative of a second partition mode into the bitstream, wherein the second partition mode allows at least one of a quad tree splitting and a binary splitting, and using the second partition mode to split the second block into a plurality of coding units (CUs), wherein the second partition mode prohibits the quad tree splitting of the second block in certain conditions.

公开(公告)号：US20230276068A1

公开(公告)日：2023-08-31

申请号：US18142173

申请日：2023-05-02

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Takashi HASHIMOTO

IPC: H04N19/52 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176

CPC classification number: H04N19/52 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in inter prediction processing: derives a first motion vector of a current block to be processed, using a motion vector of a previous block which has been previously processed; derives a second motion vector of the current block by performing motion estimation in the vicinity of the first motion vector; and generates a prediction image of the current block by performing motion compensation using the second motion vector.

公开(公告)号：US20230262231A1

公开(公告)日：2023-08-17

申请号：US18135997

申请日：2023-04-18

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH

IPC: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

CPC classification number: H04N19/159 ,  H04N19/105 ,  H04N19/176 ,  H04N19/186 ,  H04N19/583

Abstract: An encoder includes memory, and circuitry accessible to the memory. The circuitry accessible to the memory: determines whether OBMC is applicable to generation of a prediction image of a current block, according to whether BIO is to be applied to the generation of the prediction image of the current block; when BIO is to be applied to the generation of the prediction image of the current block, determines that OBMC is not applicable to the generation of the prediction image of the current block, and applies BIO to the generation of the prediction image of the current block without applying OBMC.

公开(公告)号：US20230171423A1

公开(公告)日：2023-06-01

申请号：US18103567

申请日：2023-01-31

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/513 ,  H04N19/132 ,  H04N19/176 ,  H04N19/563

CPC classification number: H04N19/513 ,  H04N19/132 ,  H04N19/176 ,  H04N19/563

Abstract: The present disclosure provides systems and methods for video coding. The systems include, for example, an image encoder comprising: circuitry; and a memory coupled to the circuitry, wherein the circuitry, in operation, performs the following: predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture; padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block; calculating at least a gradient using the second block of prediction samples; and encoding the current block using at least the calculated gradient.

公开(公告)号：US20230156214A1

公开(公告)日：2023-05-18

申请号：US18067519

申请日：2022-12-16

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Chong Soon LIM ,  Ru Ling LIAO ,  Hai Wei SUN ,  Sughosh Pavan SHASHIDHAR ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/51 ,  H04N19/176 ,  H04N19/182

CPC classification number: H04N19/51 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.

公开(公告)号：US20230119758A1

公开(公告)日：2023-04-20

申请号：US18071370

申请日：2022-11-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon LIM ,  Hai Wei SUN ,  Han Boon TEO ,  Che Wei KUO ,  Chu Tong WANG ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa Toma ,  Yusuke KATO

IPC: H04N19/117 ,  H04N19/105 ,  H04N19/119 ,  H04N19/82 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186 ,  H04N19/124

Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. In the CCALF process, in response to a coordinate of the second reconstructed image sample being (x, y), coordinates of the first reconstructed image samples are (2x, 2y−1), (2x−1, 2y), (2x, 2y), (2x+1, 2y), (2x−1, 2y+1), (2x, 2y+1), (2x+1, 2y+1), and (2x, 2y+2).