公开(公告)号：US07330052B2

公开(公告)日：2008-02-12

申请号：US11234538

申请日：2005-09-22

申请人： Sinan Kaptanoglu ,  Bruce B. Pedersen ,  James G. Schleicher ,  Jinyong Yuan ,  Michael D. Hutton ,  David Lewis

发明人： Sinan Kaptanoglu ,  Bruce B. Pedersen ,  James G. Schleicher ,  Jinyong Yuan ,  Michael D. Hutton ,  David Lewis

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/1737

摘要： A fracturable logic element includes a first, second, third, and fourth two-input lookup tables (2-LUTs). Each 2-LUT includes four memory elements. Each memory element is configured to hold one data bit. The fracturable logic element also includes a set of six inputs and a control circuit configured to operate in a first mode and a second mode. When the control circuit operates in the first mode, a first combinatorial output is generated using four of the set of six inputs and the first, second, third, and fourth 2-LUTs. When the control circuit operates in the second mode, a second combinatorial output is generated using a first subset of three of the set of six inputs and the first and second 2-LUTs. Additionally, when the control circuit operates in the second mode, a third combinatorial output is generated using a second subset of three of the set of six inputs and the third and fourth 2-LUTs, the first and second subsets being non-intersecting subsets of the set of six inputs.

摘要翻译： 可分解逻辑元件包括第一，第二，第三和第四双输入查找表（2-LUT）。 每个2-LUT包括四个存储元件。 每个存储器元件被配置为保持一个数据位。 可分解逻辑元件还包括一组六个输入和被配置为在第一模式和第二模式下操作的控制电路。 当控制电路在第一模式下工作时，使用六个输入和第一，第二，第三和第四2-LUT中的四个产生第一组合输出。 当控制电路在第二模式下操作时，使用六组输入和第一和第二2-LUT组中的三个的第一子集来生成第二组合输出。 另外，当控制电路在第二模式下工作时，使用六组输入和第三和第四2-LUT组中的三个的第二子集来产生第三组合输出，第一和第二子集是不相交的子集 一组六个输入。

公开(公告)号：US20080029606A1

公开(公告)日：2008-02-07

申请号：US11781500

申请日：2007-07-23

申请人： David Lewis

发明人： David Lewis

IPC分类号： G06K19/06

CPC分类号： G06K19/06028 ,  G06K19/06046

摘要： The present invention is a reactive bar-code element which is unreadable prior to irradiation and readable after irradiation.

摘要翻译： 本发明是一种反应性条形码元件，其在照射之前是不可读的，并且在照射之后是可读的。

公开(公告)号：US20080006798A1

公开(公告)日：2008-01-10

申请号：US11775328

申请日：2007-07-10

申请人： Richard Evans ,  Melissa Skidmore ,  Lachlan Yee ,  Tracey Hanley ,  David Lewis

发明人： Richard Evans ,  Melissa Skidmore ,  Lachlan Yee ,  Tracey Hanley ,  David Lewis

IPC分类号： G02B5/23

CPC分类号： C09D11/50 ,  C07D311/92 ,  C07F7/21 ,  C09K9/02 ,  C09K2211/1033 ,  C09K2211/1048

摘要： The invention relates to a photochromic polymeric composition comprising a polymer matrix and a photochromic compound which is an adduct comprising a photochromic moiety and at least one pendant oligomer group to provide a rate of fade of the photochromic polymeric composition which is significantly changed when compared with the corresponding composition comprising the photochromic compound without said pendent oligomer. The invention also relates to a photochromic compound which is an adduct comprising a photochromic moiety and at least one pendent oligomer.

摘要翻译： 本发明涉及一种光致变色聚合物组合物，其包含聚合物基质和光致变色化合物，其是包含光致变色部分和至少一个侧链低聚物基团的加合物，以提供光致变色聚合物组合物的褪色速率，其与 相应的组合物包含不含所述侧链低聚物的光致变色化合物。 本发明还涉及光致变色化合物，其是包含光致变色部分和至少一种侧挂低聚物的加合物。

公开(公告)号：US07312632B2

公开(公告)日：2007-12-25

申请号：US11753048

申请日：2007-05-24

申请人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

发明人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

IPC分类号： H03K19/173

CPC分类号： H03K19/17728 ,  H03K19/1737

摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexers with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

摘要翻译： 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置在包括最高级别的多路复用器的级别中，其中连接到存储器元件的输入端和连接到下一级到最高级复用器的输出的输出端和第一级多路复用器，其输入端连接到第二级 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。

公开(公告)号：US07304499B1

公开(公告)日：2007-12-04

申请号：US11454815

申请日：2006-06-16

申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz

发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/1776 ,  H03K19/17736

摘要： Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user write data. Selection circuitry, such as a multiplexer, is used to determine whether the single write path carries configuration data or user write data. In another aspect of the invention, the configuration RAM bits are used as to construct a shift register by adding pass transistors to chain the configuration RAM bits together, and clocking alternate pass transistors with two clocks 180° out of phase with one another.

摘要翻译： 可编程逻辑器件中的分布式随机存取存储器使用配置RAM位作为分布式RAM的位。 单个写入路径用于提供配置数据和用户写入数据。 选择电路，例如多路复用器，用于确定单个写入路径是否携带配置数据或用户写入数据。 在本发明的另一方面，配置RAM位用于构造移位寄存器，通过添加传输晶体管将配置RAM位链连接在一起，并且以彼此相位180°异相的两个时钟计​​时交替传输晶体管。

公开(公告)号：US20070252617A1

公开(公告)日：2007-11-01

申请号：US11743625

申请日：2007-05-02

申请人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

发明人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

IPC分类号： H03K19/177

CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.

公开(公告)号：US07283942B1

公开(公告)日：2007-10-16

申请号：US10305797

申请日：2002-11-26

申请人： David Lewis

发明人： David Lewis

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036

摘要： The present invention provides techniques for high speed electrical simulation of circuits. According to one embodiment of the present invention, a delay path can be divided into sub-paths called simulation paths. Each simulation path is simulated separately to determine its contribution to the overall delay in the path. According to another embodiment of the present invention, linear and non-linear loads are modeled using linear circuit models to further increase the speed of the simulator. According to another embodiment, driver circuits are simulated using non-linear circuit models. Before a simulation is performed, sample input and output values for the non-linear models are computed and stored in memory. When a circuit design is simulated, the input and output values are accessed from the memory. Intermediate values are determined by interpolating from the values stored memory.

摘要翻译： 本发明提供了用于电路的高速电气仿真的技术。 根据本发明的一个实施例，延迟路径可以被划分成称为模拟路径的子路径。 每个模拟路径分别进行模拟，以确定其对路径整体延迟的贡献。 根据本发明的另一个实施例，使用线性电路模型对线性和非线性负载进行建模，以进一步提高模拟器的速度。 根据另一个实施例，使用非线性电路模型来模拟驱动器电路。 在执行仿真之前，计算非线性模型的样本输入和输出值并将其存储在存储器中。 当模拟电路设计时，从存储器访问输入和输出值。 中间值通过从存储的存储器的值进行内插来确定。

公开(公告)号：US20070222477A1

公开(公告)日：2007-09-27

申请号：US11753048

申请日：2007-05-24

申请人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

发明人： David Lewis ,  Bruce Pedersen ,  Sinan Kaptanoglu ,  Andy Lee

IPC分类号： H03K19/177

CPC分类号： H03K19/17728 ,  H03K19/1737

摘要： A logic element includes memory elements, multiplexers, and controls. The multiplexers are arranged in levels including a highest level of multiplexes with inputs connected to the memory elements and outputs connected to inputs of a next-to-highest level of multiplexers and a first level of multiplexers with inputs connected to outputs of a second level of multiplexers and at least one output. The controls are connected to the multiplexers. In a first operational mode the controls determine a first-mode output at the at least one output of the first level of multiplexers, and in a second operational mode the controls determine a plurality of second-mode outputs at selected outputs of multiplexers not at the first level of multiplexers.

摘要翻译： 逻辑元件包括存储器元件，多路复用器和控制器。 多路复用器被布置成包括具有连接到存储器元件的输入的最高级复用的输出和连接到下一个到最高级多路复用器的输出的输出以及具有连接到第二级的多路复用器的输出的第一级多路复用器 多路复用器和至少一个输出。 控制器连接到多路复用器。 在第一操作模式中，所述控制确定所述第一级多路复用器的所述至少一个输出处的第一模式输出，并且在第二操作模式中，所述控制确定多路复用器的选定输出处的多个第二模式输出， 第一级多路复用器。

公开(公告)号：US07253660B1

公开(公告)日：2007-08-07

申请号：US10305886

申请日：2002-11-27

申请人： Paul Leventis ,  Bruce Pedersen ,  Chris Lane ,  Srinivas Reddy ,  David Lewis

发明人： Paul Leventis ,  Bruce Pedersen ,  Chris Lane ,  Srinivas Reddy ,  David Lewis

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K17/002

摘要： A multiplexing device is described. In one embodiment, the multiplexing device includes: a hardwired multiplexer including a plurality of input terminals; a plurality of select terminals; and at least one output terminal, where the plurality of input terminals are coupled to a plurality of block input lines or a plurality of functional element input terminals. In one embodiment, the plurality of input terminals are hardwired to the plurality of block input lines or the plurality of functional element input terminals. In one embodiment, the plurality of select terminals are coupled to a second plurality of functional element input terminals or a plurality of functional element output terminals. In one embodiment, the plurality of block input lines include a plurality of logic array block (LAB) lines, the plurality of functional element input terminals include a plurality of logic element (LE) input terminals, and the plurality of functional element output terminals include LE output terminals. In another embodiment the multiplexing device includes: a hardwired multiplexer including a plurality of data signal input terminals; and a first plurality of LEs including a first plurality of LE output terminals, where the plurality of data signal input terminals are coupled to the first plurality of LE output terminals.

摘要翻译： 描述多路复用装置。 在一个实施例中，多路复用装置包括：硬连线多路复用器，包括多个输入端; 多个选择端子; 以及至少一个输出端子，其中多个输入端子耦合到多个块输入线或多个功能元件输入端子。 在一个实施例中，多个输入端子被硬连线到多个块输入线或多个功能元件输入端子。 在一个实施例中，多个选择端子耦合到第二多个功能元件输入端子或多个功能元件输出端子。 在一个实施例中，多个块输入线包括多个逻辑阵列块（LAB）线，多个功能元件输入端包括多个逻辑元件（LE）输入端，多个功能元件输出端包括 LE输出端子。 在另一实施例中，多路复用装置包括：硬连线多路复用器，包括多个数据信号输入端; 以及包括第一多个LE输出端子的第一多个LE，其中所述多个数据信号输入端子耦合到所述第一多个LE输出端子。

公开(公告)号：USD547739S1

公开(公告)日：2007-07-31

申请号：US29261953

申请日：2006-06-21

申请人： David Lewis

设计人： David Lewis