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103 条记录 (耗时 0.019 秒)

    Distributed memory in field-programmable gate array integrated circuit devices
    1.
    发明授权
    Distributed memory in field-programmable gate array integrated circuit devices 有权
    现场可编程门阵列集成电路器件中的分布式存储器

    公开(公告)号：US07656191B2

    公开(公告)日：2010-02-02

    申请号：US12156403

    申请日：2008-05-30

    申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    IPC分类号： H03K19/177

    CPC分类号： G11C7/1045 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

    摘要翻译： 用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。 例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。 作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。 显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

    Distributed memory in field-programmable gate array integrated circuit devices
    2.
    发明申请
    Distributed memory in field-programmable gate array integrated circuit devices 有权
    现场可编程门阵列集成电路器件中的分布式存储器

    公开(公告)号：US20080231316A1

    公开(公告)日：2008-09-25

    申请号：US12156403

    申请日：2008-05-30

    申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz ,  Thomas Yau-Tsun Wong ,  Andy Lee ,  Philip Pan

    IPC分类号： H03K19/177

    CPC分类号： G11C7/1045 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1776

    摘要： Circuitry for facilitating the use of the memory elements in the look-up tables (“LUTs”) of a field programmable gate array (“FPGA”) as user-accessible, distributed RAM. For example, a register associated with a LUT and that is not needed in the read data path in user RAM mode can be used to register data for writing in user RAM mode. As another example, an otherwise unneeded register associated with a LUT can be used to provide a synchronous read address signal for user RAM mode. Several other features are shown for similarly facilitating user RAM mode with minimal (if any) additional circuitry being required in the FPGA.

    摘要翻译： 用于便于将现场可编程门阵列（“FPGA”）的查找表（“LUT”）中的存储元件用作用户可访问的分布式RAM的电路。 例如，可以使用与用户RAM模式中的与LUT相关联并且在读取数据路径中不需要的寄存器来登记用于用户RAM模式的写入数据。 作为另一示例，可以使用与LUT相关联的另外不需要的寄存器来提供用于用户RAM模式的同步读取地址信号。 显示了几个其他功能，用于在FPGA中需要最少（如果有的话）附加电路的同时方便用户RAM模式。

    Flexible I/O routing resources
    7.
    发明授权
    Flexible I/O routing resources 有权
    灵活的I / O路由资源

    公开(公告)号：US06826741B1

    公开(公告)日：2004-11-30

    申请号：US10289629

    申请日：2002-11-06

    申请人： Brian D. Johnson ,  Andy L. Lee ,  Cameron McClintock ,  Triet Nguyen ,  David Jefferson ,  Paul Leventis ,  David Lewis ,  Vaughn Betz ,  Michael Chan

    发明人： Brian D. Johnson ,  Andy L. Lee ,  Cameron McClintock ,  Triet Nguyen ,  David Jefferson ,  Paul Leventis ,  David Lewis ,  Vaughn Betz ,  Michael Chan

    IPC分类号： G06F1750

    CPC分类号： H03K19/17736 ,  H03K19/17744

    摘要： In one aspect, flexible routing resources provided are comprising an arrangement of staggered line segments on a periphery of an electronic device. In another aspect, I/O bus lines a re coupled to receive signals from and to provide signals to other bus lines, core routing, and I/O circuitry, thus facilitating the use of the I/O bus for a variety of routes that may include I/O-to-core, core-to-I/O and core-to-core routes. In another aspect, a length of I/O bus lines is optimized for speed over long signal routes with high fanout. In another aspect, the loading effects of high fanout are minimized by using a plurality of tapping buffers to couple lines to both core routing and to I/O circuitry. In another aspect, a spiraling technique is provided that allows a continuous bus having line segments of consistent length whether or not the number of I/O blocks is an integral multiple of the selected logical length for line segments.

    摘要翻译： 在一个方面，提供的灵活路由资源包括在电子设备的外围上的交错线段的布置。 在另一方面，I / O总线线路被耦合以从其接收信号并向其它总线线路，核心路由和I / O电路提供信号，从而便于将I / O总线用于各种路由， 可能包括I / O到核心，核到I / O和核心到核心的路由。 在另一方面，I / O总线的长度针对具有高扇出的长信号路由的速度被优化。 在另一方面，通过使用多个分接缓冲器来将线耦合到核心路由和I / O电路两者，高扇出的负载效应被最小化。 在另一方面，提供一种螺旋式技术，其允许具有一致长度的线段的连续总线，无论I / O块的数量是否为线段的所选逻辑长度的整数倍。

    Distributed random access memory in a programmable logic device
    9.
    发明授权
    Distributed random access memory in a programmable logic device 有权
    可编程逻辑器件中的分布式随机存取存储器

    公开(公告)号：US07304499B1

    公开(公告)日：2007-12-04

    申请号：US11454815

    申请日：2006-06-16

    申请人： David Lewis ,  Paul Leventis ,  Vaughn Betz

    发明人： David Lewis ,  Paul Leventis ,  Vaughn Betz

    IPC分类号： G06F7/38 ,  H03K19/177

    CPC分类号： H03K19/1776 ,  H03K19/17736

    摘要： Distributed random access memory in a programmable logic device uses configuration RAM bits as bits of the distributed RAM. A single write path is used to provide both configuration data and user write data. Selection circuitry, such as a multiplexer, is used to determine whether the single write path carries configuration data or user write data. In another aspect of the invention, the configuration RAM bits are used as to construct a shift register by adding pass transistors to chain the configuration RAM bits together, and clocking alternate pass transistors with two clocks 180° out of phase with one another.

    摘要翻译： 可编程逻辑器件中的分布式随机存取存储器使用配置RAM位作为分布式RAM的位。 单个写入路径用于提供配置数据和用户写入数据。 选择电路，例如多路复用器，用于确定单个写入路径是否携带配置数据或用户写入数据。 在本发明的另一方面，配置RAM位用于构造移位寄存器，通过添加传输晶体管将配置RAM位链连接在一起，并且以彼此相位180°异相的两个时钟计​​时交替传输晶体管。

    VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK
    10.
    发明申请
    VERSATILE LOGIC ELEMENT AND LOGIC ARRAY BLOCK 有权

    公开(公告)号：US20070252617A1

    公开(公告)日：2007-11-01

    申请号：US11743625

    申请日：2007-05-02

    申请人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    发明人： David Lewis ,  Paul Leventis ,  Andy Lee ,  Henry Kim ,  Bruce Pedersen ,  Chris Wysocki ,  Christopher Lane ,  ALexander Marquardt ,  Vikram Santurkar ,  Vaughn Betz

    IPC分类号： H03K19/177

    CPC分类号： H03K19/17764 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736

    摘要： An embodiment of this invention pertains to a versatile and flexible logic element and logic array block (“LAB”). Each logic element includes a programmable combinational logic function block such as a lookup table (“LUT”) and a flip-flop. Within the logic element, multiplexers are provided to allow the flip-flop and the LUT to be programmably connected such that either the output of the LUT may be connected to the input of the flip-flop or the output of the flip-flop may be connected to the input of the LUT. An additional multiplexer allows the output of the flip-flop in one logic element to be connected to the input of a flip-flop in a different logic element within the same LAB. Output multiplexers selects between the output of the LUT and the output of the flip-flop to generate signals that drive routing lines within the LAB and to routing lines external to the LAB. These output multiplexers are constructed such that the combinational output (output from the LUT) is faster than the output from the flip-flop. A collection of routing lines and multiplexers within the LAB are used to provide inputs to the LUTs. Each of the input multiplexers for each logic element is connected to a subset of the routing lines within the LAB using a specific pattern of connectivity of multiplexers to associated wires that maximizes the efficiency of use of the routing wires. Control signals for the set of logic elements within the LAB are generated using a secondary signal generation unit that minimizes contention for shared signals. One of the control signals is an “add-or-subtract control signal” that allows all of the LEs in a LAB to perform either addition or subtraction under the control of a logic signal. In a PLD supporting redundancy, the carry chain for the LABs is arranged in the same direction that redundancy shifts to remap defective LABs and a multiplexer on the carry input of a LAB is used to select the appropriate carry output from another LAB depending on whether redundancy is engaged.