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108 条记录 (耗时 0.026 秒)

    Four port RAM cell
    93.
    发明授权
    Four port RAM cell 有权
    四端口RAM单元

    公开(公告)号：US06741517B1

    公开(公告)日：2004-05-25

    申请号：US10113684

    申请日：2002-03-29

    申请人： Duncan M. Fisher ,  Rajiv Gupta

    发明人： Duncan M. Fisher ,  Rajiv Gupta

    IPC分类号： G11C800

    CPC分类号： G11C8/16

    摘要： According to one embodiment, a RAM array includes at least one RAM cell comprising a first access transistor driven by a first word line. When the first access transistor is turned on, it couples the RAM cell to a first bit line. The first bit line is connected to a single-ended sense amplifier such as an inverter. Similarly, the RAM cell comprises second, third, and fourth access transistors driven by respectively second, third, and fourth word lines. When the respective access transistors are turned on, they couple the RAM cell to respectively second, third, and fourth bit lines. The bit lines are connected to respective single-ended sense amplifiers such as inverters. In one embodiment, each of the first, second, third, and fourth access transistors is an NFET. The first, second, third, and fourth bit lines are coupled to respectively first, second, third, and fourth precharge transistors.

    摘要翻译： 根据一个实施例，RAM阵列包括至少一个RAM单元，包括由第一字线驱动的第一存取晶体管。 当第一存取晶体管导通时，它将RAM单元耦合到第一位线。 第一位线连接到诸如逆变器的单端读出放大器。 类似地，RAM单元包括分别由第二，第三和第四字线驱动的第二，第三和第四存取晶体管。 当相应的存取晶体管导通时，它们将RAM单元分别耦合到第二，第三和第四位线。 位线连接到相应的单端读出放大器，如逆变器。 在一个实施例中，第一，第二，第三和第四存取晶体管中的每一个是NFET。 第一，第二，第三和第四位线分别耦合到第一，第二，第三和第四预充电晶体管。

    Copied register files for data processors having many execution units
    94.
    发明授权
    Copied register files for data processors having many execution units 失效
    具有多个执行单位的数据处理器的复制寄存器文件

    公开(公告)号：US06629232B1

    公开(公告)日：2003-09-30

    申请号：US09609911

    申请日：2000-07-03

    申请人： Ken Arora ,  Harshvardhan Sharangpani ,  Rajiv Gupta

    发明人： Ken Arora ,  Harshvardhan Sharangpani ,  Rajiv Gupta

    IPC分类号： G06F1300

    CPC分类号： G06F9/3012 ,  G06F9/30141 ,  G06F9/3885 ,  G06F9/3891

    摘要： Interconnect-dominated large register files are reduced in chip area and delay time. A register file in a processor having a number of execution units is divided into multiple copies. Different groups of execution units can read from and write to their own copy of the file registers by a set of local read and write ports. All of the register-file copies are synchronized by writing data from the execution units to remote write ports in at least some registers in other copies of the register file. Each copy can be divided into local and global registers. While all copies of the global registers continue to be written by the remote write ports, the local registers can be written only by a local cluster of execution units. Alternatively or additionally, all of the execution units can write to their local register-file copy, but only some of the units can write the global registers in all copies of the register file.

    摘要翻译： 互连主导的大型寄存器文件在芯片面积和延迟时间上都有所减少。 具有多个执行单元的处理器中的寄存器文件被分成多个副本。 不同的执行单元组可以通过一组本地读写端口读取和写入其自己的文件寄存器副本。 所有寄存器文件副本都通过将数据从执行单元写入到寄存器文件的其他副本的至少一些寄存器中的远程写入端口来同步。 每个副本可分为本地和全局寄存器。 虽然全局寄存器的所有副本仍然由远程写入端口写入，但本地寄存器只能由本地执行单元集群写入。 或者或另外，所有执行单元都可以写入其本地寄存器文件副本，但只有一些单元可以将全局寄存器写入寄存器文件的所有副本。

    Multi-threaded processing system and method for scheduling the execution of threads based on data received from a cache memory
    95.
    发明授权
    Multi-threaded processing system and method for scheduling the execution of threads based on data received from a cache memory 失效
    多线程处理系统和方法，用于根据从高速缓冲存储器接收的数据来调度线程的执行

    公开(公告)号：US06578065B1

    公开(公告)日：2003-06-10

    申请号：US09405441

    申请日：1999-09-23

    申请人： Robert Aglietti ,  Tomas G. Rokicki ,  Rajiv Gupta

    发明人： Robert Aglietti ,  Tomas G. Rokicki ,  Rajiv Gupta

    IPC分类号： G06F900

    CPC分类号： G06F9/4881 ,  G06F9/3851

    摘要： A system and method for controlling the scheduling of threads in a multi-thread processor system. The multi-thread processor system has a multi-thread processor, a main memory, a cache memory, and a thread scheduler. Information is sent from the cache memory to the thread scheduler for determining which thread the processor is going to execute. The thread scheduler calculates or maintains a figure of merit for each thread executing on the processor. The figure of merit determines which thread to switch to when the current or previous thread has a long latency. The figure of merit define the execution environment as measured by the performance of the cache memory. The figure of merit can be the owner of a particular thread, the number of data lines accessed by a particular thread which resides in the cache, the number of times a particular thread has hit in the cache over a specified time interval, the thread that installed the data or the thread that was used most recently.

    摘要翻译： 一种用于控制多线程处理器系统中的线程调度的系统和方法。 多线程处理器系统具有多线程处理器，主存储器，高速缓冲存储器和线程调度器。 信息从高速缓冲存储器发送到线程调度器，以确定处理器将执行哪个线程。 线程调度器计算或维护在处理器上执行的每个线程的品质因数。 当当前或之前的线程具有较长的延迟时，品质因数决定了切换到哪个线程。 品质因数定义了由高速缓冲存储器的性能测量的执行环境。 品质因数可以是特定线程的所有者，由驻留在缓存中的特定线程访问的数据线的数量，特定线程在指定时间间隔内在高速缓存中的次数，线程 安装了最近使用的数据或线程。

    Resource access control in a software system
    96.
    发明授权
    Resource access control in a software system 失效
    软件系统中的资源访问控制

    公开(公告)号：US06470339B1

    公开(公告)日：2002-10-22

    申请号：US09281876

    申请日：1999-03-31

    申请人： Alan H. Karp ,  Rajiv Gupta ,  Arindam Banerji ,  Chia-Chiang Chao ,  Ernest Mak ,  Sandeep Kumar ,  Venkatesh Krishnan ,  Guillermo Rozas

    发明人： Alan H. Karp ,  Rajiv Gupta ,  Arindam Banerji ,  Chia-Chiang Chao ,  Ernest Mak ,  Sandeep Kumar ,  Venkatesh Krishnan ,  Guillermo Rozas

    IPC分类号： G06F1700

    CPC分类号： G06F9/468 ,  Y10S707/99938 ,  Y10S707/99939

    摘要： A software system that provides access control to resources and that disassociates access rights to resources from references to resources to prevent the formation of large and unwieldy access control lists and to enable advanced decentralized security controls. The software system includes a repository that holds a resource descriptor for each resource including lock/permission pairs. Access to particular resources or groups of resources is provided by providing users with the appropriate keys. The keys are themselves are resources with resource descriptors in the repository. Access rights for users may be revoked by deleting keys from the repository. The software system also provides visibility fields for compartmentalizing access to resources. In addition, the software system provides authorizers that maintain audit trails when critical resource such as keys are passed among users and that enable advanced security control when passing resources among users.

    摘要翻译： 一种提供对资源的访问控制以及将资源的访问权限从资源引用分解的软件系统，以防止形成大而笨重的访问控制列表并实现高级分散安全控制。 该软件系统包括一个存储库，其中包含包含锁/权限对的每个资源的资源描述符。 通过向用户提供适当的密钥来提供对特定资源或资源组的访问。 密钥本身就是存储库中资源描述符的资源。 可以通过从存储库中删除密钥来撤消对用户的访问权限。 软件系统还提供可视化领域，用于区分对资源的访问。 此外，软件系统提供授权人员，当关键资源（如密钥在用户中传递）之间时，可以维护审计跟踪，并且在用户之间传递资源时可实现高级安全控制。

    Optimizing computer performance by using data compression principles to minimize a loss function
    97.
    发明授权
    Optimizing computer performance by using data compression principles to minimize a loss function 失效
    通过使用数据压缩原理优化计算机性能，以最大限度地减少损失

    公开(公告)号：US06453389B1

    公开(公告)日：2002-09-17

    申请号：US09340279

    申请日：1999-06-25

    申请人： Marcelo Weinberger ,  Tomas G. Rokicki ,  Gadiel Seroussi ,  Rajiv Gupta ,  Neri Merhav ,  Joesp M. Ferrandiz

    发明人： Marcelo Weinberger ,  Tomas G. Rokicki ,  Gadiel Seroussi ,  Rajiv Gupta ,  Neri Merhav ,  Joesp M. Ferrandiz

    IPC分类号： G06F1200

    CPC分类号： G06F12/0862 ,  G06F2212/6026

    摘要： The method of prefetching data into cache to minimize CPU stall time uses a rough predictor to make rough predictions about what cache lines will be needed next by the CPU. The address difference generator uses the rough prediction and the actual cache miss address to determine the address difference. The prefetch engine builds a data structure to represent address differences and weights them according to the accumulated stall time produced by the cache misses given that the corresponding address is not prefetched. This stall time is modeled as a loss function of the form: L = ∑ j = 0 n ⁢   ⁢ L ⁢   ⁢ ( x j ) L ⁢   ⁢ ( x j ) = ∑ i = 0 sl ⁡ ( j ) - 1 ⁢   ⁢ C i ⁢   ⁢ ( b j - i , x j ) The weights in the data structure change as the prefetch engine learns more information. The prefetch engine's goal is to predict the cache line needed and prefetch before the CPU requests it.

    摘要翻译： 将数据预取到缓存中以最小化CPU停顿时间的方法使用粗略的预测器来粗略地预测CPU将需要什么高速缓存行。 地址差产生器使用粗略预测和实际高速缓存未命中地址来确定地址差异。 预取引擎构建数据结构以表示地址差异，并根据缓存未命中产生的累积停顿时间来加权它们，因为相应地址未被预取。 该失速时间被建模为形式的损失函数：数据结构中的权重随着预取引擎学习更多信息而改变。 预取引擎的目标是在CPU请求之前预测所需的高速缓存行和预取。

    Quantitative analysis system and method for certifying ultrasound medical imaging equipment
    98.
    发明授权
    Quantitative analysis system and method for certifying ultrasound medical imaging equipment 失效
    超声医学影像设备认证的定量分析系统和方法

    公开(公告)号：US06370480B1

    公开(公告)日：2002-04-09

    申请号：US09316011

    申请日：1999-05-21

    申请人： Rajiv Gupta ,  Yibin Zheng ,  Christopher James Dailey

    发明人： Rajiv Gupta ,  Yibin Zheng ,  Christopher James Dailey

    IPC分类号： G01B7008

    CPC分类号： G01S7/5205 ,  A61B8/00 ,  A61B8/587 ,  G06T7/0002 ,  G06T2207/30168

    摘要： An analysis system and method provide for quantitatively evaluating image quality characteristics of an ultrasound imaging machine that evaluates at least one image representation of a standard phantom acquired by the image machine. The machine under test by comparing acquired parameters with prestored values, and returning a determined set of image quality indices, along with a single index representing an arithmetic combination of all other image quality indices, which indicate the accuracy of the test image relative to a “gold standard” that has been pre-established for the model of imaging machine under investigation. The system, which includes a computer-programmed set of instructions and data, optionally includes at least one standard phantom. The image quality indices, or metrics, quantitatively represent an evaluation of a test image using a set of relatively subjective criteria that include homogeneity, contrast, signal attenuation and penetration of depth, pin to background ratio in near and far-field, axial and lateral resolution, modulation transfer function, and geometric distortion, and axial and lateral linearity. These image quality indices are determined by specific algorithms and then combined to form an image health index. The image health index and the individual component indices are compared to a gold standard set of indices obtained from an equivalent imaging machine operating under optimum conditions and settings.

    摘要翻译： 分析系统和方法提供用于定量评估超声成像机的图像质量特征，所述超声成像机评估图像机获取的标准体模的至少一个图像表示。 通过将获取的参数与预先存储的值进行比较，并且返回确定的图像质量指标集合以及表示所有其他图像质量指标的算术组合的单个指标，测试该机器，其指示测试图像相对于“ 黄金标准“，已经为被调查的成像机模型预先建立。 该系统包括计算机编程的指令和数据集，可选地包括至少一个标准体模。 图像质量指标或度量定量地表示使用一组相对主观标准来评估测试图像，该组相对主观标准包括深度的深度，纵向和远场，轴向和横向的深度，针对背景比的均匀性，对比度，信号衰减和穿透 分辨率，调制传递函数和几何失真，以及轴向和横向线性度。 这些图像质量指标由特定算法确定，然后组合形成图像健康指数。 将图像健康指数和各个组分指数与从最佳条件和设置下运行的等效成像机获得的黄金标准指标进行比较。

    Three dimensional locally adaptive warping for volumetric registration of images
    99.
    发明授权
    Three dimensional locally adaptive warping for volumetric registration of images 有权
    图像体积注册的三维局部自适应翘曲

    公开(公告)号：US06154518A

    公开(公告)日：2000-11-28

    申请号：US186029

    申请日：1998-11-04

    申请人： Rajiv Gupta

    发明人： Rajiv Gupta

    IPC分类号： A61B6/00 ,  G06T3/00 ,  G06T7/00 ,  G01N23/04

    CPC分类号： G06T7/0026 ,  G06T3/0081 ,  G06T7/0038 ,  G06T2207/30101

    摘要： Locally-adaptive, sub-voxel registration of two volumetric data sets is performed by generating match points and then, using the match points, generating a locally-adaptive image-to-warp transformation. Generation of the match points is accelerated by generating a volume hierarchy and then identifying a set of 3D points in the first volume for designation as interesting points. Interesting points in the first volume are then matched with their corresponding points in the second volume. After performing match point generation, points on a cubic grid in the first volume are matched to the corresponding match points in the second volume by resampling the match points on the cubic grid in the first volume. After a grid of match points has been identified, the displacement (dx, dy, dz) that should be added to each cubic grid point in the first volume to identify the coordinates of the corresponding point in the second volume is determined. Using the displacements in the match points, a warping transformation function that specifies the displacement for each point (x, y, z) in the first volume is determined. The transformation function maps the matched points in the first volume to corresponding points in the second volume by determining the amount of displacement in the x, y and z directions.

    摘要翻译： 通过产生匹配点，然后使用匹配点，产生局部自适应的图像到翘曲变换来执行两个体数据集的局部自适应，子体素注册。 生成匹配点通过生成卷层次结构加速，然后识别第一卷中的一组3D点，用于指定为有趣点。 然后将第一卷中的有趣点与第二卷中的相应点相匹配。 在执行匹配点生成之后，通过对第一卷中的立方网格上的匹配点进行重新采样，将第一卷中的立方网格上的点与第二卷中的对应匹配点匹配。 在确定了匹配点网格之后，确定应该添加到第一卷中的每个立方网格点的位移（dx，dy，dz）以识别第二卷中对应点的坐标。 使用匹配点中的位移，确定指定第一体积中每个点（x，y，z）的位移的翘曲变换函数。 变换函数通过确定x，y和z方向上的位移量，将第一个体积中的匹配点映射到第二个体积中的相应点。