公开(公告)号：US20050067645A1

公开(公告)日：2005-03-31

申请号：US10738999

申请日：2003-12-19

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  H01L21/768 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115

CPC分类号： H01L27/11507 ,  H01L21/76895 ,  H01L27/11502

摘要： First and second ferroelectric capacitors are selectively connected with a first bit line. Data is read to the first bit line from a first ferroelectric capacitor by applying a first voltage in a coordinate increasing direction of an axis or from the second ferroelectric capacitor by applying a second voltage having a sign opposite to the first voltage in the coordinate increasing direction. Third and fourth ferroelectric capacitors are selectively connected with a second bit line. Data is read to the second bit line from the third ferroelectric capacitor by applying a third voltage having the same sign as the first voltage in the coordinate increasing direction or from the fourth ferroelectric capacitor by applying a fourth voltage having the same sign as the second voltage in the coordinate increasing direction. A sense amplifier amplifies the potential difference between the first and second bit lines.

摘要翻译： 第一和第二铁电电容器选择性地与第一位线连接。 通过在坐标增加方向施加具有与第一电压相反的符号的第二电压，通过在轴的坐标增加方向上施加第一电压或从第二铁电电容器向第一位线读取数据到第一位线 。 第三和第四铁电电容器选择性地与第二位线连接。 通过施加具有与第二电压相同的符号的第四电压，通过施加具有与坐标增加方向上的第一电压相同的符号的第三电压或从第四铁电电容器向第二位线读取数据到第二位线 在坐标增加方向。 读出放大器放大第一和第二位线之间的电位差。

公开(公告)号：US07872899B2

公开(公告)日：2011-01-18

申请号：US11902873

申请日：2007-09-26

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： The memory cell array includes a memory cell, the memory cell including a ferroelectric capacitor and a transistor. The memory cell array includes a word line selecting the memory cell, a plate line applying a drive voltage to the ferroelectric capacitor, and a bit line reading data from the ferroelectric capacitor. A selection transistor selectively connects the memory cell to the bit line. A dummy cell provides a reference potential, the reference potential being referred to for a potential read from the memory cell. A sense amplifier circuit includes a plurality of amplification circuits amplifying the potential difference between a bit-line pair. A decoupling circuit electrically cuts off the bit line between the amplification circuits.

摘要翻译： 存储单元阵列包括存储单元，存储单元包括铁电电容器和晶体管。 存储单元阵列包括选择存储单元的字线，向铁电电容器施加驱动电压的板线和从铁电电容器读取数据的位线。 选择晶体管选择性地将存储单元连接到位线。 虚拟单元提供参考电位，参考电位参考从存储单元读取的电位。 读出放大器电路包括放大位线对之间的电位差的多个放大电路。 去耦电路电切断放大电路之间的位线。

公开(公告)号：US20050013156A1

公开(公告)日：2005-01-20

申请号：US10721420

申请日：2003-11-26

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105

CPC分类号： G11C11/22

摘要： A semiconductor integrated circuit device includes unit cells, memory cell blocks, bit lines, word lines, block select signal lines, plate lines, and a plate line driver. The unit cell includes a cell transistor and a ferroelectric capacitor connected between a source and a drain of the cell transistor. The memory cell block includes the unit cells connected in series between a first terminal and a second terminal and a block select transistor connected between the second terminal and a third terminal. The bit line connects commonly the third terminals of the blocks. The word line connects commonly gates of cell transistors in the blocks. The block select signal line connects commonly gates of block select transistors in the blocks. The plate line connects commonly the first terminals of the blocks. The plate line driver is connected to the plate lines and applies a potential to the plate lines.

摘要翻译： 半导体集成电路装置包括单位单元，存储单元块，位线，字线，块选择信号线，板线和板线驱动器。 单元电池包括连接在单元晶体管的源极和漏极之间的单元晶体管和铁电电容器。 存储单元块包括串联连接在第一端子和第二端子之间的单元电池以及连接在第二端子和第三端子之间的块选择晶体管。 位线通常连接块的第三个端子。 字线连接块中的单元晶体管的通用栅极。 块选择信号线连接块中的块选择晶体管的共同门。 板线通常连接块的第一个端子。 板线驱动器连接到板条线并向板线施加电位。

公开(公告)号：US06816399B2

公开(公告)日：2004-11-09

申请号：US10400565

申请日：2003-03-28

申请人： Katsuhiko Hoya ,  Daisaburo Takashima

发明人： Katsuhiko Hoya ,  Daisaburo Takashima

IPC分类号： G11C1122

CPC分类号： H01L27/11502

摘要： A semiconductor memory device includes a memory cell block, gate lines and branch lines. The memory cell block includes memory cells connected in series. Each of memory cells has a cell transistor having a source and a drain and a ferroelectric capacitor inbetween the source and the drain. The gate lines are connected to the gates of the cell transistors of the memory cell block. The gate lines have a predetermined width and are arranged at regular intervals. The branch lines are formed of a layer different from that of the gate lines, arranged parallel to the gate lines, and each connected thereto. The branch lines have a predetermined width and are arranged at regular intervals. The sum of the width of the branch lines and the interval between adjacent branch lines differing from the sum of the width of the gate lines and the interval between adjacent gate lines.

摘要翻译： 半导体存储器件包括存储器单元块，栅极线和分支线。 存储单元块包括串联连接的存储器单元。 每个存储单元具有在源极和漏极之间具有源极和漏极的电池晶体管和铁电电容器。 栅极线连接到存储单元块的单元晶体管的栅极。 栅极线具有预定的宽度并且以规则的间隔布置。 分支线由与栅极线平行的栅极线的层不同的层形成，并且各自与栅极线连接。 分支线具有预定的宽度并且以规则的间隔布置。 分支线的宽度和相邻支线之间的间隔与栅极线的宽度和相邻栅极线之间的间隔之和不同的总和。

公开(公告)号：US08792266B2

公开(公告)日：2014-07-29

申请号：US13605674

申请日：2012-09-06

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： A memory cell is formed with a resistance variable element, which is interposed between first and second electrodes and can store resistance changes representing 2 or more different values, and first and second cell transistors having source terminals thereof connected to the first electrode, and gates thereof to a word line. A drain of the first cell transistor is connected to a bit line, and a drain of the second cell transistor is connected to a data line. The second electrode is connected to a source line. During a read operation, the first and second cell transistors are kept in an ON state, and a current is supplied from the bit line to the source line through the memory cell. Data is read according to the electrical potential difference between the data line and the source line.

摘要翻译： 存储单元形成有电阻可变元件，其被插入在第一和第二电极之间，并且可以存储表示2个或更多个不同值的电阻变化，以及其源极端子连接到第一电极的第一和第二单元晶体管及其栅极 到一个字线。 第一单元晶体管的漏极连接到位线，并且第二单元晶体管的漏极连接到数据线。 第二电极连接到源极线。 在读取操作期间，第一和第二单元晶体管保持在导通状态，并且通过存储单元从位线向源极线提供电流。 根据数据线和源极线之间的电位差读取数据。

公开(公告)号：US08650373B2

公开(公告)日：2014-02-11

申请号：US12860160

申请日：2010-08-20

申请人： Kosuke Hatsuda ,  Daisaburo Takashima

发明人： Kosuke Hatsuda ,  Daisaburo Takashima

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F11/1441

摘要： According to one embodiment, a memory system includes a nonvolatile first memory, a nonvolatile second memory, a data-copy processing unit and a data invalidation processing unit. The first memory has a storage capacity for n (n≧2) pages per word line. The nonvolatile second memory temporarily stores user data write-requested from a host apparatus. The data-copy processing unit executes data copy processing including reading out, in page units, the user data stored in the second memory and sequentially writing the read-out user data in page units in the first memory. The data invalidation processing unit selects, after the execution of the data copy processing, based on whether the memory cell group per word line stores user data for n pages, user data requiring backup out of the user data subjected to the data copy processing and leaves the selected user data in the second memory as backup data.

摘要翻译： 根据一个实施例，存储器系统包括非易失性第一存储器，非易失性第二存储器，数据复制处理单元和数据无效化处理单元。 第一个存储器具有每个字线n（n> = 2）页的存储容量。 非易失性第二存储器临时存储从主机装置写入请求的用户数据。 数据复制处理单元执行数据复制处理，包括以页为单位读出存储在第二存储器中的用户数据，并以页单元顺序地将读出的用户数据写入第一存储器。 数据无效处理单元在执行数据复制处理之后，根据每个字线的存储单元组是否存储n页的用户数据，选择需要备份的用户数据进行数据复制处理的用户数据，并且离开 所选择的用户数据在第二存储器中作为备份数据。

公开(公告)号：US08559223B2

公开(公告)日：2013-10-15

申请号：US13049504

申请日：2011-03-16

申请人： Daisaburo Takashima

发明人： Daisaburo Takashima

IPC分类号： G11C11/40

CPC分类号： G11C14/0018 ,  G11C14/00 ,  G11C16/04 ,  G11C16/0408 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11529

摘要： According to one embodiment, there is provided a fusion memory including a first memory cell array formed of a NAND cell unit and a second memory cell array formed of a DRAM cell on a semiconductor substrate. The NAND cell unit is formed of a non-volatile memory cell having a two-layer gate structure in which a first gate and a second gate are stacked, and a selective transistor connecting the first and second gates of the non-volatile memory cell. The DRAM cell is formed of a cell transistor having a structure same as the structure of the selective transistor, and a MOS capacitor having a structure same as the structure of the non-volatile memory cell or the selective transistor.

摘要翻译： 根据一个实施例，提供了一种融合存储器，包括由NAND单元单元形成的第一存储单元阵列和由半导体衬底上的DRAM单元形成的第二存储单元阵列。 NAND单元单元由具有堆叠第一栅极和第二栅极的双层栅极结构的非易失性存储单元和连接非易失性存储单元的第一和第二栅极的选择晶体管构成。 DRAM单元由具有与选择晶体管的结构相同的单元晶体管和具有与非易失性存储单元或选择晶体管的结构相同的结构的MOS电容器形成。

公开(公告)号：US08255762B2

公开(公告)日：2012-08-28

申请号：US13297327

申请日：2011-11-16

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda

IPC分类号： H03M13/00

CPC分类号： G11C16/349 ,  G06F11/1068 ,  G11C11/005 ,  G11C16/3431

摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.

摘要翻译： 本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取的数据被写回同一个存储器组时，当错误位计数超过第一阈值时 或者当数据读取计数超过第二阈值时。

公开(公告)号：US08156393B2

公开(公告)日：2012-04-10

申请号：US12513860

申请日：2007-11-28

申请人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

发明人： Yasushi Nagadomi ,  Daisaburo Takashima ,  Kosuke Hatsuda ,  Shinichi Kanno

IPC分类号： G11C29/00

CPC分类号： G11C16/349 ,  G06F11/008 ,  G06F11/1068

摘要： To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

摘要翻译： 提供一种确定诸如耗尽水平的存储器状态并且允许有效地使用存储器的存储器系统。 存储器系统包括NAND型闪速存储器1，数据可以被电写入/擦除;非易失性存储器2，对NAND型闪速存储器1的擦除操作次数进行计数，并保持擦除次数和最大数量 擦除操作，以及控制器3，其具有从计算机4被给予自诊断命令的连接接口31，并且基于自身检测从非易失性存储器2检索擦除操作的次数和擦除操作的最大次数， 诊断命令，并通过连接接口31输出擦除操作次数和最大擦除次数。

公开(公告)号：US08134349B2

公开(公告)日：2012-03-13

申请号：US12404438

申请日：2009-03-16

申请人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

发明人： Hidehiro Shiga ,  Shinichiro Shiratake ,  Daisaburo Takashima

IPC分类号： G05F1/613

CPC分类号： G05F1/56

摘要： A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.

摘要翻译： 电源电路具有恒压电路，第一MOS晶体管，第二MOS晶体管，第三MOS晶体管，第一分压电路，输出通过将输出端子的电压除以第一分压而得到的第一分压 以及馈送有参考电压的第一差分放大器电路和第一分压，并且具有连接到第二MOS晶体管的栅极的输出。 当第一分压高于参考电压时，第一差分放大器电路输出信号以接通第二MOS晶体管，并且当第一分压电压较低时，第一差分放大器电路输出关闭第二MOS晶体管的信号 比参考电压。