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91.发明授权System and method for dynamically executing a function in a programmable logic array 失效用于在可编程逻辑阵列中动态执行功能的系统和方法公开(公告)号：US07750670B2
公开(公告)日：2010-07-06
申请号：US12185467
申请日：2008-08-04
申请人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Jack R. Smith , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Jack R. Smith , Sebastian T. Ventrone
IPC分类号： H03K19/173
CPC分类号： H03K19/17752 , G06F15/7867 , H03K19/17756 , H03K19/1776
摘要： A reconfigurable logic array (RLA) having a logic capacity and configured to process a function having a total logic requirement that exceeds the logic capacity of the RLA. The RLA includes first and second storage regions and a plurality of programmable logic elements located between the first and second storage regions. When the function is parsed into a plurality of functional blocks, this configuration allows the RLA to process the function by sequentially processing the functional blocks in alternating directions within the RLA, using the plurality of programmable logic elements to sequentially process each of the functional blocks and using the first and second storage regions to temporarily hold the input and output for that one of the functional blocks.
摘要翻译： 具有逻辑容量并被配置为处理具有超过RLA的逻辑容量的总逻辑要求的功能的可重构逻辑阵列（RLA）。 RLA包括第一和第二存储区域以及位于第一和第二存储区域之间的多个可编程逻辑元件。 当功能被解析成多个功能块时，该配置允许RLA通过在RLA内沿交替方向依次处理功能块来处理功能，使用多个可编程逻辑元件来顺序地处理每个功能块和 使用第一和第二存储区域临时保持该功能块的输入和输出。
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92.发明授权System for method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly 有权用于在间歇电力环境中预测电力事件的方法的系统，并相应地调度集成电路的计算操作公开(公告)号：US07732949B2
公开(公告)日：2010-06-08
申请号：US11550573
申请日：2006-10-18
CPC分类号： C09K11/77 , G06F1/3203
摘要： A system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.
摘要翻译： 一种在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的系统和方法。 功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路 。 一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，基于历史日志预测随后的功率事件，检索一个或者 更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。
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93.发明申请公开(公告)号：US20090125744A1
公开(公告)日：2009-05-14
申请号：US11938899
申请日：2007-11-13
IPC分类号： G06F1/28
CPC分类号： G06F1/3203 , G06F1/3287 , Y02D10/171
摘要： A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.
摘要翻译： 一种用于系统的设计结构以及在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的方法。 功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路 。 一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，基于历史日志预测随后的功率事件，检索一个或者 更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。
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公开(公告)号：US20080212977A1
公开(公告)日：2008-09-04
申请号：US11772378
申请日：2007-07-02
申请人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
发明人： Gary R. Doyle , Kenneth J. Goodnow , Riyon W. Harding , Francis A. Kampf , Jason M. Norman , Sebastian T. Ventrone
IPC分类号： H04B10/00
CPC分类号： G02B6/43
摘要： An optical transmission method. Signal transmissions between cores of an integrated circuit are performed. Each signal transmission is between two cores of a different pair of cores of the integrated circuit. Each signal transmission includes transmission of an optical signal in the visible or infrared portion of the electromagnetic spectrum at a wavelength that is specific to each different pair of cores and is a different wavelength for each different pair of cores. There is no overhead for decoding or arbitration in preforming the signal transmissions that would otherwise exist if a same wavelength for the optical signals were permitted for pairs of cores of the different pairs of cores.
摘要翻译： 光传输方法。 执行集成电路的核心之间的信号传输。 每个信号传输在集成电路的不同核心的两个核之间。 每个信号传输包括以对于每个不同的核对特定的波长的电磁光谱的可见光或红外部分中的光信号的传输，并且对于每个不同的一对核心是不同的波长。 如果对于不同核心对的核对允许相同的光信号波长，则在进行信号传输时，没有解码或仲裁的开销。
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公开(公告)号：US07107469B2
公开(公告)日：2006-09-12
申请号：US10604328
申请日：2003-07-11
CPC分类号： G06F1/3203 , G06F1/3287 , G11C5/144 , G11C5/147 , G11C2207/2227 , Y02D10/171
摘要： A structure and associated method of processing data on a semi-conductor device comprising an input island, a processing island, and an output island formed on the semiconductor device. The input island is adapted to accept a specified amount of data and enable a means for providing a first specified voltage for powering the processing island after accepting the specified amount of data. The processing island is adapted to receive and process the specified amount of data from the input island upon powering the processing island by the first specified voltage. The output island is adapted to be powered by a second specified voltage. The processing island is further adapted to transmit the processed data to the output island upon said powering by the second specified voltage. The first specified voltage is adapted to be disabled thereby removing power from processing island upon completion of transmission of the processed data to the output island.
摘要翻译： 一种在半导体器件上处理数据的结构和相关方法，包括形成在半导体器件上的输入岛，处理岛和输出岛。 输入岛适于接收指定数量的数据，并且能够在接受指定数量的数据之后启用用于提供用于为处理岛供电的第一指定电压的装置。 处理岛适于在对处理岛供电第一指定电压时从输入岛接收和处理指定量的数据。 输出岛适于由第二规定电压供电。 处理岛还适于在所述第二规定电压的供电时将经处理的数据发送到输出岛。 第一指定电压适于被禁用，从而在完成将处理的数据传输到输出岛时从处理岛去除功率。
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公开(公告)号：US06825711B2
公开(公告)日：2004-11-30
申请号：US10249684
申请日：2003-04-30
IPC分类号： G05F110
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.
摘要翻译： 一种集成电路，方法和系统，提供更精细的粒度动态电压控制，无需性能损失。 本发明提供了用于在特定周期中动态地改变关键路径上的至少一个级的电压电平的装置。 以这种方式，可以为给定期望的阶段提供最佳电压。
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97.发明授权公开(公告)号：US06275968B1
公开(公告)日：2001-08-14
申请号：US09129921
申请日：1998-08-06
IPC分类号： G06F1750
CPC分类号： G06F1/32 , G06F1/04 , G06F17/505
摘要： According to the preferred embodiment, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded toggling that commonly occurs in many types of logic circuits. The preferred embodiment reduces unneeded node toggling in a circuit by holding a portion of the device at the previous output until the all the inputs have stabilized to their final value during each clock cycle. This reduces power consumption in the device that would normally occur due to unnecessary node toggling.
摘要翻译： 根据优选实施例，提供了一种通过减少不需要的节点切换来降低功耗的装置和方法。 优选实施例减少了通常在许多类型的逻辑电路中发生的不必要的切换。 优选实施例通过将设备的一部分保持在先前输出来减少电路中的不需要的节点切换，直到所有输入在每个时钟周期内稳定到其最终值。 这减少了由于不必要的节点切换而通常发生的设备中的功耗。
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98.发明授权Apparatus and method for efficient battery utilization in portable personal computers 失效便携式个人计算机中有效利用电池的装置和方法
公开(公告)号：US6167524A
公开(公告)日：2000-12-26
申请号：US56300
申请日：1998-04-06
申请人： Kenneth J. Goodnow , Michel S. Michail , Janak G. Patel , Wilbur D. Pricer , Sebastian T. Ventrone
发明人： Kenneth J. Goodnow , Michel S. Michail , Janak G. Patel , Wilbur D. Pricer , Sebastian T. Ventrone
CPC分类号： G06F9/3885 , G06F1/3203 , G06F1/3287 , G06F9/3836 , G06F9/3842 , G06F9/3869 , Y02D10/171
摘要： An apparatus and method controlling power consumption in portable personal computers by dynamically allocating power to the system logic. Expected total power consumption is calculated and compared to an optimum power efficiency value. The expected power consumption values for each execution unit are stored in a look-up table in actual or compressed form. If the expected total power consumption value exceeds the power efficiency value, selected execution units are made inactive. Conversely, if the power efficiency value exceeds the expected total power consumption value, execution unit functions are added in order to maintain a level current demand on the battery.
摘要翻译： 一种通过动态分配系统逻辑电力来控制便携式个人计算机中的功耗的装置和方法。 计算总功耗，并将其与最佳功率效率值进行比较。 每个执行单元的预期功耗值以实际或压缩形式存储在查找表中。 如果预期的总功耗值超过功率效率值，则使所选择的执行单元无效。 相反，如果功率效率值超过预期的总功耗值，则添加执行单元功能以便保持对电池的电平电流需求。
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公开(公告)号：US6097241A
公开(公告)日：2000-08-01
申请号：US159898
申请日：1998-09-24
CPC分类号： G06F1/3203 , G06F1/3296 , Y02B60/1285
摘要： An integrated circuit such as an ASIC device having partitioned functional units with independent threshold voltage control. A first partition is always operated in a normal mode, while subsequent partitions are maintained in a standby mode until a transition is detected at the input of the first partition. The subsequent partitions are switched to the normal mode by lowering the body voltage applied to the devices with each partition. A pulse stretcher is used to keep a partition in a normal mode for a predetermined period of time after the transition is detected.
摘要翻译： 诸如具有独立阈值电压控制的具有分区功能单元的ASIC器件的集成电路。 第一分区总是以正常模式操作，而后续分区保持在待机模式，直到在第一分区的输入处检测到转换。 随后的分区通过降低施加到每个分区的设备的体电压而切换到正常模式。 在检测到转换之后，使用脉冲展开器将分区保持在正常模式下预定的时间段。
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100.发明授权公开(公告)号：US07937560B2
公开(公告)日：2011-05-03
申请号：US12121292
申请日：2008-05-15
申请人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
发明人： Kerry Bernstein , Kenneth J. Goodnow , Clarence R. Ogilvie , Christopher B. Reynolds , Sebastian T. Ventrone , Keith R. Williams
CPC分类号： G06F9/3867 , G06F1/32 , G06F1/3287 , G06F11/1407 , G06F11/1441 , Y02D10/171
摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.
摘要翻译： 公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点产生逻辑，该参考节点是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。
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