公开(公告)号：US4719478A

公开(公告)日：1988-01-12

申请号：US910727

申请日：1986-09-23

申请人： Masayoshi Tachihara ,  Shinichi Hirasawa ,  Masami Ikeda ,  Akira Asai ,  Hirokazu Komuro

发明人： Masayoshi Tachihara ,  Shinichi Hirasawa ,  Masami Ikeda ,  Akira Asai ,  Hirokazu Komuro

IPC分类号： B41J2/14 ,  G01D15/16

CPC分类号： B41J2/14129 ,  B41J2/1412 ,  B41J2202/11

摘要： A planar heat generating resistor has a heat generating resistor layer formed on or above a support member and a pair of opposing electrodes formed on the heat generating resistor layer, such that a width of the heat generating layer at the electrode area is larger than a width of the electrodes and a voltage is applied across the electrodes, in which a ratio of a maximum value of a gradient of .phi., .sqroot.(.differential..phi./.differential.x).sup.2 +(.differential..phi./.differential.y).sup.2 to a value of .sqroot.(.differential..phi./.differential.x).sup.2 +(.differential..phi./.differential.y).sup.2 at a center of the resistor is no larger than 1.4 when a Laplace equation .differential..sup.2 /.differential.x.sup.2 +.differential..sup.2 .phi./.differential.y.sup.2 =0 is solved for the heat generating resistor when an orthogonal coordinate system X-Y is defined on the resistor surface, a potential at a point (x,y) on the resistor surface is represented by .phi.(x,y), a boundary value is imparted to an area of a circumferential boundary of the resistor which contacts to one of the electrodes, a different boundary value is imparted to an area which contacts to the other electrode, and a boundary condition in which a differential coefficient of .phi. to a normal direction of the circumferential boundary is zero is imparted to an area which does not contact to any of the electrodes.

摘要翻译： 平面发热电阻器具有形成在支撑构件上或上方的发热电阻层和形成在发热电阻层上的一对相对电极，使得电极区域处的发热层的宽度大于宽度 的电极上施加电压，其中phi，2ROOT（DIFFERENTIAL phi / DIFFERENTIAL x）2（DIFFERENTIAL phi / DIFFERENTIAL y）2的梯度的最大值与2ROOT值的比值 当求解拉普拉斯方程差分2 /差分x2 +差分2比特/差分y2 = 0时，电阻中心处的差分phi /差分x）2+（差分phi /差分y）2不大于1.4 电阻器，当电阻表面上定义正交坐标系XY时，电阻表面上的点（x，y）处的电位由phi（x，y）表示，边界值被赋予圆周边界的区域 与电极之一接触的电阻器，赋予与另一个电极接触的区域不同的边界值，并且赋予与周向边界的法线方向的微分系数为零的边界条件 到不与任何电极接触的区域。

公开(公告)号：US4283150A

公开(公告)日：1981-08-11

申请号：US38845

申请日：1979-05-14

申请人： Masami Hanazono ,  Tomoyoshi Watanabe ,  Toshio Nakai ,  Susumu Kuzuya ,  Akira Asai ,  Takayuki Iwase ,  Kazuo Nakamura ,  Hiroshi Onoda

发明人： Masami Hanazono ,  Tomoyoshi Watanabe ,  Toshio Nakai ,  Susumu Kuzuya ,  Akira Asai ,  Takayuki Iwase ,  Kazuo Nakamura ,  Hiroshi Onoda

IPC分类号： B41J5/18 ,  B41J5/22 ,  B41J7/30 ,  B41J7/96 ,  B41J23/04 ,  B41J23/02

CPC分类号： B41J7/30 ,  B41J7/96

摘要： An electric typewriter having a prevention mechanism for preventing printing errors caused by a depression of a few keys in very rapid succession. The prevention mechanism includes a lock member for locking a clutch, which is interposed between a drive motor and a printing mechanism, in a disengaged condition. The lock member is normally held in a non-operational position for allowing the clutch to be engaged, and is moved in response to a special operation of a sensing member to an operational position for keeping the clutch in a disengaged condition. The sensing member is so disposed as to be moved in a distinct way different from the normal operation mode when a few keys have been depressed in very rapid succession.

摘要翻译： 一种具有预防机构的电动打字机，其用于防止因非常快速的连续按压几个按键引起的打印错误。 防止机构包括用于锁定离合器的锁定构件，该离合器介于驱动马达和打印机构之间，处于脱离状态。 锁定构件通常保持在非操作位置以允许离合器接合，并且响应于感测构件的特殊操作而移动到用于将离合器保持在脱离状态的操作位置。 感测构件被布置成当以非常快速的连续按压几个键时以与正常操作模式不同的不同方式移动。

公开(公告)号：US4234262A

公开(公告)日：1980-11-18

申请号：US26676

申请日：1979-04-03

申请人： Toshio Nakai ,  Susumu Kuzuya ,  Akira Asai ,  Takayuki Iwase ,  Hiroshi Onoda ,  Kazuo Nakamura

发明人： Toshio Nakai ,  Susumu Kuzuya ,  Akira Asai ,  Takayuki Iwase ,  Hiroshi Onoda ,  Kazuo Nakamura

IPC分类号： B41J1/60

CPC分类号： B41J1/60 ,  Y10T403/604

摘要： A single element print head having an apparatus for firmly and releasably attaching itself to the drive shaft of a typewriter. The body of the print head is provided with a central opening therethrough for receipt of the drive shaft. A cap is secured on the body around one end of the opening with the purpose of slidably holding a manual slide member in its guide recess and fixedly holding a base portion of a hair pin shaped spring in its holding groove. The spring has a pair of arms for firmly fastening therebetween, and for releasing the drive shaft by virtue of its resilience and the action of a pair of cam surfaces. The pair of cam surfaces are formed in the bottom portion of the slide member, diverging from one end to the other end like a front portion of a bullet, for expanding the arms from each other to release the arms from the drive shaft by means of the slide movement of the slide member.

摘要翻译： 单元件打印头具有用于牢固且可释放地将自身附接到打字机的驱动轴上的装置。 打印头的主体设置有穿过其的中心开口，用于接收驱动轴。 盖子围绕开口的一端被固定在主体上，目的是在其引导凹槽中可滑动地保持手动滑动构件，并将发夹形弹簧的基部固定地保持在其保持槽中。 弹簧具有用于牢固地紧固在其间的一对臂，并且由于其弹性和一对凸轮表面的作用来释放驱动轴。 一对凸轮表面形成在滑动构件的底部，如同子弹的前部从一端向另一端分叉，用于使臂互相扩张，以使臂从驱动轴通过 滑动构件的滑动运动。

公开(公告)号：US07473967B2

公开(公告)日：2009-01-06

申请号：US10558671

申请日：2004-05-31

申请人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

发明人： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Yoshihiko Kanzawa ,  Kouji Katayama ,  Junko Iwanaga

IPC分类号： H01L27/088

CPC分类号： H01L29/785 ,  H01L29/66795 ,  H01L29/78687

摘要： A semiconductor device according to this invention includes: a first insulating layer (11); a first body section (13) including an island-shaped semiconductor formed on the first insulating layer; a second body section (14) including an island-shaped semiconductor formed on the first insulating layer; a ridge-shaped connecting section (15) formed on the first insulating layer to interconnect the first body section and the second body section; a channel region (15a) formed by at least a part of the connecting section in lengthwise direction of the connecting section; a gate electrode (18) formed to cover a periphery of the channel region, with a second insulating layer intervening therebetween; a source region formed to extend over the first body section and a portion of the connecting section between the first body section and the channel region; and a drain region formed to extend over the second body section and a portion of the connecting section between the second body section and the channel region, wherein a semiconductor forming the channel region has a lattice strain.

摘要翻译： 根据本发明的半导体器件包括：第一绝缘层（11）; 第一主体部分（13），其包括形成在所述第一绝缘层上的岛状半导体; 包括形成在所述第一绝缘层上的岛状半导体的第二主体部分（14） 形成在第一绝缘层上以互连第一主体部分和第二主体部分的脊形连接部分（15）; 由连接部的长度方向的至少一部分形成的通道区域（15a）; 形成为覆盖沟道区域的周边的栅极电极（18），其间插入有第二绝缘层; 形成为在第一主体部分上延伸的源极区域和在第一主体部分和沟道区域之间的连接部分的一部分; 以及形成为在第二主体部分上延伸的漏极区域和在第二主体部分和沟道区域之间的连接部分的一部分，其中形成沟道区域的半导体具有晶格应变。

公开(公告)号：US07244972B2

公开(公告)日：2007-07-17

申请号：US10868774

申请日：2004-06-17

申请人： Minoru Kubo ,  Yo Ichikawa ,  Akira Asai ,  Takahiro Kawashima

发明人： Minoru Kubo ,  Yo Ichikawa ,  Akira Asai ,  Takahiro Kawashima

IPC分类号： H01L29/778

CPC分类号： H01L29/518 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/318 ,  H01L21/8213 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/802

摘要： In a field effect transistor, an Si layer 11, an SiC (Si1−yCy) channel layer 12, a CN gate insulating film 13 made of a carbon nitride layer (CN) and a gate electrode 14 are deposited in this order on an Si substrate 10. The thickness of the SiC channel layer 12 is set to a value that is less than or equal to the critical thickness so that a dislocation due to a strain does not occur according to the carbon content. A source region 15 and a drain region 16 are formed on opposite sides of the SiC channel layer 12, and a source electrode 17 and a drain electrode 18 are provided on the source region 15 and the drain region 16, respectively.

摘要翻译： 在场效应晶体管中，Si层11，SiC（Si 1-y C y）沟道层12，由氮化碳制成的CN栅极绝缘膜13 层（CN）和栅电极14依次沉积在Si衬底10上。 将SiC沟道层12的厚度设定为小于或等于临界厚度的值，使得根据碳含量不会发生由于应变引起的位错。 源极区域15和漏极区域16形成在SiC沟道层12的相对侧上，源极电极17和漏极电极18分别设置在源极区域15和漏极区域16上。

公开(公告)号：US07197440B2

公开(公告)日：2007-03-27

申请号：US10192159

申请日：2002-07-11

申请人： Shigeki Matsutani ,  Akira Asai

发明人： Shigeki Matsutani ,  Akira Asai

IPC分类号： G06F17/10 ,  G06F9/44

CPC分类号： G06F17/5018

摘要： It provides a finite element method library which improves the reliability of a program using the finite element method as a library, and avoids calculation errors and an increase in convergence time due to programming errors. To this end, a library that describes a program process based on the finite element method is characterized in that a vector of a vector space spanned by basis functions of the finite element method, and a dual vector of a dual vector space defined by a metric derived from an inner product which is determined by the square integrations of the basis functions, are defined as different abstract data types.

摘要翻译： 它提供了一种有限元方法库，它使用有限元方法作为库来提高程序的可靠性，并避免计算错误和由于编程错误引起的收敛时间的增加。 为此，描述基于有限元方法的程序过程的库的特征在于，由有限元方法的基函数跨越的向量空间的向量和由度量定义的双向量空间的双向量 从由基函数的平方积分确定的内积产生的，被定义为不同的抽象数据类型。

公开(公告)号：US07087473B2

公开(公告)日：2006-08-08

申请号：US10866093

申请日：2004-06-14

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L29/80

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US20060086988A1

公开(公告)日：2006-04-27

申请号：US11294566

申请日：2005-12-06

申请人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

发明人： Haruyuki Sorada ,  Akira Asai ,  Takeshi Takagi ,  Akira Inoue ,  Yoshio Kawashima

IPC分类号： H01L21/8238 ,  H01L29/94

CPC分类号： H01L21/823807

摘要： A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transistor are eventually formed in the pair of first device forming regions and the pair of second device forming regions, respectively.

摘要翻译： 根据本发明的半导体集成电路制造方法包括：通过器件隔离来围绕每个区域来在半导体衬底的表面层部分中形成一对第一器件形成区域和一对第二器件形成区域的步骤; 在前述步骤之后形成覆盖半导体衬底的表面的第一氧化物膜的步骤; 去除所述第一氧化物膜的预期部分以暴露所述一对第二器件形成区域的步骤; 通过选择性外延生长形成一对异质结结构在由此露出的一对第二器件形成区上的步骤; 在上述步骤之后形成覆盖基板表面的第二氧化膜的步骤; 以及在所述一对第一器件形成区域和所述一对第二器件形成区域中的每一个上形成一对栅电极的步骤，由此在所述一对第一器件形成区域中最终形成正常互补MOS晶体管和异质结互补MOS晶体管 形成区域和一对第二装置形成区域。

公开(公告)号：US06917075B2

公开(公告)日：2005-07-12

申请号：US10752409

申请日：2004-01-07

申请人： Akira Inoue ,  Akira Asai ,  Teruhito Ohnishi ,  Haruyuki Sorada ,  Yoshihiro Hara ,  Takeshi Takagi

发明人： Akira Inoue ,  Akira Asai ,  Teruhito Ohnishi ,  Haruyuki Sorada ,  Yoshihiro Hara ,  Takeshi Takagi

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/78 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66772 ,  H01L21/76895 ,  H01L29/783 ,  H01L29/78615 ,  H01L29/78621

摘要： A semiconductor device and a method of fabricating the same according to this invention are such that: a gate insulator is formed over a predetermined region of a semiconductor substrate; a gate electrode is formed on the gate insulator; source and drain regions respectively formed in portions of the predetermined region that are situated on both sides of the gate electrode in plan view; a body region formed by a region of the predetermined region exclusive of the source and drain regions; and a contact electrically interconnecting the gate electrode and the body region, wherein a portion of the contact which is connected to the gate electrode is formed to intersect the gate electrode in plan view.

摘要翻译： 根据本发明的半导体器件及其制造方法是：在半导体衬底的预定区域上形成栅极绝缘体; 栅电极形成在栅极绝缘体上; 源极和漏极区域分别形成在预定区域的位于栅极电极的两侧的部分中; 由不同于所述源极和漏极区域的所述预定区域的区域形成的体区; 以及使所述栅电极和所述体区域电连接的触点，其中，与所述栅电极连接的所述触点的一部分在平面图中形成为与所述栅电极相交。

公开(公告)号：US20050087764A1

公开(公告)日：2005-04-28

申请号：US10978513

申请日：2004-11-02

申请人： Akira Inoue ,  Takeshi Takagi ,  Akira Asai ,  Haruyuki Sorada

发明人： Akira Inoue ,  Takeshi Takagi ,  Akira Asai ,  Haruyuki Sorada

IPC分类号： H01J29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L31/0336

CPC分类号： H01L21/28123 ,  H01L29/1054 ,  H01L29/1087 ,  H01L29/4238 ,  H01L29/66651 ,  H01L29/783

摘要： A MISFET according to this invention includes: a substrate having a semiconductor layer; an active region formed in the semiconductor layer; a gate insulator formed on the active region; a gate formed on the gate insulator; and a source region and a drain region, wherein: the active region is formed, in plan view, to have a body portion and a projecting portion projecting from a periphery of the body portion; the gate is formed, in plan view, to intersect the body portion of the active region, cover a pair of connecting portions connecting a periphery of the projecting portion to the periphery of the body portion and allow a part of the projecting portion to project from a periphery of the gate; and the source region and the drain region are formed in regions of the body portion of the active region which are situated on opposite sides of the gate in plan view, respectively.

摘要翻译： 根据本发明的MISFET包括：具有半导体层的衬底; 形成在半导体层中的有源区; 形成在有源区上的栅极绝缘体; 形成在栅极绝缘体上的栅极; 源极区域和漏极区域，其中：有源区域在平面图中形成为具有从主体部分的周边突出的主体部分和突出部分; 在平面图中，门形成为与有源区域的主体部分相交，覆盖将突出部分的周边连接到主体部分的周边的一对连接部分，并使突出部分的一部分从 门的周边; 并且源极区域和漏极区域分别形成在有源区域的主体部分的位于平面图的栅极的相对侧上的区域中。