公开(公告)号：US11551969B2

公开(公告)日：2023-01-10

申请号：US17199085

申请日：2021-03-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L21/02 ,  H01L23/535

Abstract: An integrated circuit (IC) structure includes a transistor, a front-side interconnection structure, a backside via, and a backside interconnection structure. The transistor includes a source/drain epitaxial structure. The front-side interconnection structure is on a front-side of the transistor. The backside via is connected to the source/drain epitaxial structure of the transistor. The backside interconnection structure is connected to the backside via and includes a conductive feature, a dielectric layer, and a spacer structure. The conductive feature is connected to the backside via. The dielectric layer laterally surrounds the conductive feature. The spacer structure is between the conductive feature and the dielectric layer and has an air gap.

公开(公告)号：US11532714B2

公开(公告)日：2022-12-20

申请号：US17093345

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L23/48 ,  H01L21/8234 ,  H01L23/528

Abstract: A device includes a device layer including a first transistor, a first interconnect structure on a front-side of the device layer, and a second interconnect structure on a backside of the device layer. The second interconnect structure includes a first dielectric material on the backside of the device layer, a contact extending through the first dielectric material to a first source/drain region of the first transistor, and a first conductive layer including a first conductive line electrically connected to the first source/drain region through the contact.

公开(公告)号：US11532713B2

公开(公告)日：2022-12-20

申请号：US17091159

申请日：2020-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: A device includes a device layer comprising a first transistor and a second transistor; a first interconnect structure on a front-side of the device layer; and a second interconnect structure on a backside of the device layer. The second interconnect structure comprising a first dielectric layer on the backside of the device layer, wherein a semiconductor material is disposed between the first dielectric layer and a first source/drain region of the first transistor; a contact extending through the first dielectric layer to a second source/drain region of the second transistor; and a first conductive line electrically connected to the second source/drain region of the second transistor through the contact.

公开(公告)号：US11502201B2

公开(公告)日：2022-11-15

申请号：US17081915

申请日：2020-10-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Shih-Chuan Chiu ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/417 ,  H01L29/49 ,  H01L29/66

Abstract: A semiconductor device structure includes a source/drain feature comprising a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, a dielectric layer in contact with the second surface of the source/drain feature, a semiconductor layer having a first surface, a second surface opposing the first surface, and a sidewall connecting the first surface to the second surface, wherein the sidewall of the semiconductor layer is in contact with the sidewall of the source/drain feature, and the second surface of the semiconductor layer is co-planar with the second surface of the source/drain feature, and a gate structure having a surface in contact with the first surface of the semiconductor layer.

公开(公告)号：US11456209B2

公开(公告)日：2022-09-27

申请号：US17092773

申请日：2020-11-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: Semiconductor devices including air spacers formed in a backside interconnect structure and methods of forming the same are disclosed. In an embodiment, a device includes a first transistor structure; a front-side interconnect structure on a front-side of the first transistor structure; and a backside interconnect structure on a backside of the first transistor structure, the backside interconnect structure including a first dielectric layer on the backside of the first transistor structure; a first via extending through the first dielectric layer, the first via being electrically coupled to a first source/drain region of the first transistor structure; a first conductive line electrically coupled to the first via; and an air spacer adjacent the first conductive line, the first conductive line defining a first side boundary of the air spacer.

公开(公告)号：US11380682B2

公开(公告)日：2022-07-05

申请号：US16360502

申请日：2019-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Huan-Chieh Su ,  Zhi-Chang Lin ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L21/8234

Abstract: Examples of an integrated circuit with FinFET devices and a method for forming the integrated circuit are provided herein. In some examples, an integrated circuit device includes a substrate, a fin extending from the substrate, a gate disposed on a first side of the fin, and a gate spacer disposed alongside the gate. The gate spacer has a first portion extending along the gate that has a first width and a second portion extending above the first gate that has a second width that is greater than the first width. In some such examples, the second portion of the gate spacer includes a gate spacer layer disposed on the gate.

公开(公告)号：US20210376081A1

公开(公告)日：2021-12-02

申请号：US17402985

申请日：2021-08-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Chiang ,  Huan-Chieh Su ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/308 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/40 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L21/762 ,  H01L29/10

Abstract: A method of forming a semiconductor device includes forming semiconductor strips protruding above a substrate and isolation regions between the semiconductor strips; forming hybrid fins on the isolation regions, the hybrid fins comprising dielectric fins and dielectric structures over the dielectric fins; forming a dummy gate structure over the semiconductor strip; forming source/drain regions over the semiconductor strips and on opposing sides of the dummy gate structure; forming nanowires under the dummy gate structure, where the nanowires are over and aligned with respective semiconductor strips, and the source/drain regions are at opposing ends of the nanowires, where the hybrid fins extend further from the substrate than the nanowires; after forming the nanowires, reducing widths of center portions of the hybrid fins while keeping widths of end portions of the hybrid fins unchanged, and forming an electrically conductive material around the nanowires.

公开(公告)号：US20210375691A1

公开(公告)日：2021-12-02

申请号：US16888217

申请日：2020-05-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Yuan Chen ,  Huan-Chieh Su ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/8234 ,  H01L27/088 ,  H01L23/528 ,  H01L29/417 ,  H01L21/764 ,  H01L21/3105 ,  H01L21/02

Abstract: A method includes providing a structure having transistors, an isolation structure over the transistors, metal plugs through the isolation structure and connecting to the transistors, and a trench with the isolation structure and the metal plugs as sidewalls. The method further includes forming a dielectric liner on the sidewalls of the trench and over the isolation structure and the metal plugs. The dielectric liner is thicker at an opening portion of the trench than at another portion of the trench so that an air gap is formed inside the trench and the air gap is surrounded by the dielectric liner. The method further includes depositing a sacrificial layer over the dielectric liner and over the air gap and performing CMP to remove the sacrificial layer and to recess the dielectric liner until the isolation structure and the metal plugs are exposed. The air gap remains inside the trench.

公开(公告)号：US20210336020A1

公开(公告)日：2021-10-28

申请号：US16984881

申请日：2020-08-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Li-Zhen Yu ,  Huan-Chieh Su ,  Lin-Yu Huang ,  Cheng-Chi Chuang ,  Chih-Hao Wang

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8234

Abstract: Methods of forming backside vias connected to source/drain regions of long-channel semiconductor devices and short-channel semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first transistor structure; a second transistor structure adjacent the first transistor structure; a first interconnect structure on a front-side of the first transistor structure and the second transistor structure; and a second interconnect structure on a backside of the first transistor structure and the second transistor structure, the second interconnect structure including a first dielectric layer on the backside of the first transistor structure; a second dielectric layer on the backside of the second transistor structure; a first contact extending through the first dielectric layer and electrically coupled to a first source/drain region of the first transistor structure; and a second contact extending through the second dielectric layer and electrically coupled to a second source/drain region of the second transistor structure, the second contact having a second length less than a first length of the first contact.

公开(公告)号：US20210273075A1

公开(公告)日：2021-09-02

申请号：US17091767

申请日：2020-11-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan-Ting Pan ,  Huan-Chieh Su ,  Jia-Chuan You ,  Shi Ning Ju ,  Kuo-Cheng Chiang ,  Yi-Ruei Jhan ,  Li-Yang Chuang ,  Chih-Hao Wang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/8234

Abstract: A semiconductor structure includes a plurality of fin structures extending along a first direction, a plurality of gate structure segments positioned along a line extending in a second direction, the second direction being orthogonal to the first direction, wherein the gate structure segments are separated by dummy fin structures. The semiconductor structure further includes a conductive layer disposed over both the gate structure segments and the dummy fin structures to electrically connect at least some of the gate structure segments, and a cut feature aligned with one of the dummy fin structures and positioned to electrically isolate gate structure segments on both sides of the one of the dummy fin structures.