公开(公告)号：US20090160848A1

公开(公告)日：2009-06-25

申请号：US12314909

申请日：2008-12-18

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： G09G5/00 ,  H03L5/00

CPC分类号： H03K3/356139

摘要： Disclosed is a level shift circuit including a first level shift circuit that is connected between a first power supply terminal and first and second output terminals and receives first and second input signals from the first and second input terminals, respectively, and sets one of the first and second output terminals to a first voltage level, based on the first and second input signals; a second level shift circuit that is connected between a second power supply terminal and the first and second output terminals, and sets the other of the first and second terminals to a second voltage level; and a circuit that performs control to disconnect a current path in the second level shifter between the second power supply terminal and one of the first and second output terminals that is driven to the second voltage level at a time point when the first and second input signals are supplied to the first and second input terminals for a predetermined period including the time point when the first and second input signals are supplied to the first and second input terminals, and to cancel the disconnection of the current path in the second level shifter between the one output terminal and the second power supply terminal after the predetermined period. Output amplitudes at the first and second output terminals are set to be larger than amplitudes of the first and second input signals.

摘要翻译： 公开了一种电平移位电路，包括第一电平移位电路，其连接在第一电源端子和第一和第二输出端子之间，并分别从第一和第二输入端子接收第一和第二输入信号，并且设置第一 并且基于所述第一和第二输入信号将所述第二输出端子设置到第一电压电平; 第二电平移位电路，连接在第二电源端子与第一和第二输出端子之间，并将第一和第二端子中的另一个设置为第二电压电平; 以及电路，其执行控制以断开所述第二电平转换器之间的电流路径，所述电流路径在所述第二电源端子与所述第一和第二输入信号之间的时间点被驱动到所述第二电压电平的所述第一和第二输出端子中的一个之间 在包括第一和第二输入信号被提供给第一和第二输入端的时间点的预定时段内被提供给第一和第二输入端，并且消除第二电平移位器中的电流路径的断开 一个输出端子和第二电源端子。 将第一和第二输出端子处的输出幅度设置为大于第一和第二输入信号的幅度。

公开(公告)号：US20080174462A1

公开(公告)日：2008-07-24

申请号：US11979342

申请日：2007-11-01

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03M1/66 ,  H03K3/00 ,  G06F3/038

CPC分类号： H03M1/742 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/0291 ,  G09G2330/021

摘要： Disclosed is a data driver including a positive-polarity reference voltage generation circuit that outputs positive-polarity reference voltages, a positive-polarity decoder that receives the positive-polarity reference voltages from the positive-polarity reference voltage generation circuit, and selects and outputs at least one positive-polarity reference voltage in accordance with first digital data, a positive-polarity amplifier which includes a first differential units that receives the selected reference voltage selected by the positive-polarity decoder, performs amplification, and outputs a voltage to a first amplifier output terminal, a negative-polarity reference voltage generation circuit that outputs negative-polarity reference voltages, a negative-polarity decoder that receives the negative-polarity reference voltages from the negative-polarity reference voltage generation circuit, and selects and outputs at least one negative-polarity reference voltage in accordance with second digital data, a negative-polarity amplifier which includes a second differential unit that receives the reference voltage selected by the negative-polarity decoder, performs amplification, and outputs a voltage to a second amplifier output terminal, and an output switch circuit that straightly connects the first and second amplifier output terminals to first and second driver output terminals, respectively, or cross-connects the first and second amplifier output terminals to the second and first driver output terminals, respectively. The data driver is provided with an intermediate voltage supply, in addition to a high voltage supply and a low voltage supply. To the positive-polarity amplifier excluding a differential unit, a high-potential voltage supply and an intermediate-potential voltage supply are provided. The high-potential voltage supply and a low-potential voltage supply are provided to the differential unit. To the negative-polarity amplifier excluding a differential unit, the intermediate-potential voltage supply and the low-potential voltage supply are provided. The high-potential voltage supply and the low-potential voltage supply are provided to the differential unit.

公开(公告)号：US20080122776A1

公开(公告)日：2008-05-29

申请号：US11979351

申请日：2007-11-01

申请人： Junichirou Ishii ,  Hiroshi Tsuchi

发明人： Junichirou Ishii ,  Hiroshi Tsuchi

IPC分类号： G09G3/36 ,  H03H1/00

CPC分类号： G09G3/3688 ,  G09G3/2011 ,  G09G3/3696

摘要： A multilevel voltage generating circuit includes first and second input nodes provided on a first resistance element and supplied with first and second reference voltages. A current substantially flows in a first specific area for a line between the first and second input nodes based on a difference between the first and second reference voltages. A first group of output nodes are provided for the first resistance element to output a portion of a plurality of level voltages. A first one of the first group of output nodes for one of the plurality of level voltages which is closest to the first reference voltage is provided outside the first specific area. The first output node, the first input node, and the second input node, are arranged on a line on the first resistance element in this order.

摘要翻译： 多电平电压产生电路包括设置在第一电阻元件上并被提供有第一和第二参考电压的第一和第二输入节点。 基于第一和第二参考电压之间的差，电流基本上流过第一和第二输入节点之间的线的第一特定区域。 为第一电阻元件提供第一组输出节点以输出多个电平电压的一部分。 在第一特定区域的外部设置与第一参考电压最接近的多个电平电压中的一个的第一组输出节点中的第一组。 第一输出节点，第一输入节点和第二输入节点依次排列在第一电阻元件的一行上。

公开(公告)号：US07369075B2

公开(公告)日：2008-05-06

申请号：US11300387

申请日：2005-12-15

申请人： Junichirou Ishii ,  Hiroshi Tsuchi

发明人： Junichirou Ishii ,  Hiroshi Tsuchi

IPC分类号： H03M1/66

CPC分类号： H03M1/76

摘要： An output circuit, a digital/analog conversion circuit and a display apparatus can reduce the number of required input voltages and the number of transistors to save the necessary area. The output circuit and the digital/analog conversion circuit comprise a selection circuit for receiving as input a plurality of (m) reference voltages having mutually different respective voltage values, selecting two of the voltages according to a selection signal and outputting them and an amplifier circuit for receiving as input the voltages output from the selection circuit at two input terminals T1, T2 and outputting the voltage obtained by interpolating the voltage difference of the two input terminal voltages V(T1), V(T2) to a predetermined ratio. It may alternatively be so arranged that the selection circuit sequentially outputs the selected two voltages and the amplifier circuit sequentially receives as two input the two voltages and outputs the output voltage obtained by interpolation.

摘要翻译： 输出电路，数字/模拟转换电路和显示装置可以减少所需输入电压的数量和晶体管的数量以节省必要的面积。 输出电路和数字/模拟转换电路包括一个选择电路，用于接收具有相互不同的相应电压值的多个（m）个参考电压作为输入，根据选择信号选择两个电压并输出它们，以及一个放大器电路 用于从两个输入端子T 1，T 2处输入从选择电路输出的电压，并将通过将两个输入端子电压V（T 1），V（T 2）的电压差内插到预定的 比。 或者，可选地，选择电路顺序地输出所选择的两个电压，并且放大器电路依次接收两个电压作为两个输入，并输出通过插值获得的输出电压。

公开(公告)号：US07342527B2

公开(公告)日：2008-03-11

申请号：US11408045

申请日：2006-04-21

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03M1/66

CPC分类号： H03M1/662 ,  G09G3/3688 ,  G09G2310/027 ,  H03M1/76

摘要： Disclosed is a digital-to-analog converting circuit including: a reference voltage generating circuit for outputting a plurality of reference voltages having voltage values that differ from one another; a data input control circuit for exercising control based upon a control signal so as to output either one of even-numbered bits or odd-numbered bits and then the other of the even-numbered bits or odd-numbered bits from a multiple-bit digital data signal input thereto; a decoder for successively selecting first and second voltages, inclusive of voltages that are identical, from among the plurality of reference voltages, which are output from the reference voltage generating circuit, in accordance with an output signal from the data input control circuit, and outputting the selected first and second voltages successively to the single terminal; and a differential amplifier, receiving the first and second voltages output from the decoder successively from the single terminal, for outputting from an output terminal an output voltage obtained by externally dividing the first and second voltages at a predetermined prescribed external ratio.

摘要翻译： 公开了一种数模转换电路，包括：基准电压发生电路，用于输出具有彼此不同的电压值的多个参考电压; 数据输入控制电路，用于基于控制信号进行控制，以便输出偶数位或奇数位之一，然后从多位数字中输出偶数位或奇数位中的另一位 数据信号输入; 解码器，用于根据来自数据输入控制电路的输出信号连续地选择包括从参考电压产生电路输出的多个参考电压中的相同的第一和第二电压，并输出 选择的第一和第二电压连续地连接到单个端子; 以及差分放大器，从所述单个端子连续地接收从所述解码器输出的所述第一和第二电压，以从输出端口输出以预定的规定的外部比率从外部除去所述第一和第二电压而获得的输出电压。

公开(公告)号：US20070205807A1

公开(公告)日：2007-09-06

申请号：US11680669

申请日：2007-03-01

申请人： Hiroshi Tsuchi ,  Osamu Ishibashi

发明人： Hiroshi Tsuchi ,  Osamu Ishibashi

IPC分类号： G01R19/00

CPC分类号： G11C7/065 ,  G11C7/08

摘要： The amplifier includes first and second inverters that form a flip-flop. In this flip-flop, an input of first inverter is connected to an output of the second inverter, and an output of the first inverter is connected to an input of the second inverter. Control terminals of at least one transistors (MN1, MN2) of first and second transistor pairs (MP1, MN1 and MP2, MN2) that constitute first and second inverters, respectively, are connected to inputs of first and second inverters through first and second capacitances (C1, C2), respectively. At resetting, inputs (1, 2) and outputs (OUT, OUTB) of first and second inverters are not mutually cross-connected, wherein a reference signal (VR) is supplied in common to inputs (1, 2) of the first and second inverters. The one transistors (MN1, MN2) are diode-connected. Voltage differences between reference signal (VR) and respective control terminals of the one transistors are stored in the first and second capacitances (C1, C2), respectively. At signal input, diode connections of the one transistors (MN1, MN2) are released. Inputs (1, 2) of the first and second inverters are disconnected from the reference signal. First and second input signals (S1, S2) are supplied to inputs (1, 2), respectively. Then, inputs and outputs of first and second inverters are mutually cross-connected, forming the flip-flop. The amplifier with high-speed and highly reliable operation does not depend on variations in devices therein.

摘要翻译： 放大器包括形成触发器的第一和第二反相器。 在该触发器中，第一反相器的输入连接到第二反相器的输出端，第一反相器的输出端连接到第二反相器的输入。 构成第一和第二反相器的第一和第二晶体管对（MP 1，MN 1和MP 2，MN 2）的至少一个晶体管（MN 1，MN 2）的控制端分别连接到第一和第二 逆变器分别通过第一和第二电容（C 1，C 2）。 在复位时，第一和第二反相器的输入（1,2）和输出（OUT，OUTB）不互相交叉，其中参考信号（VR）被共同提供给第一和第二反相器的输入（1,2） 第二台逆变器。 一个晶体管（MN 1，MN 2）是二极管连接的。 参考信号（VR）和一个晶体管的各控制端之间的电压差分别存储在第一和第二电容（C 1，C 2）中。 在信号输入端，一个晶体管（MN 1，MN 2）的二极管连接被释放。 第一和第二逆变器的输入（1,2）与参考信号断开。 第一和第二输入信号（S1，S2）分别被提供给输入（1,2）。 然后，第一和第二反相器的输入和输出相互交叉连接，形成触发器。 具有高速和高可靠运行的放大器不依赖于其中的器件的变化。

公开(公告)号：US20070194377A1

公开(公告)日：2007-08-23

申请号：US11740226

申请日：2007-04-25

申请人： Kenji Sera ,  Hiroshi Tsuchi

发明人： Kenji Sera ,  Hiroshi Tsuchi

IPC分类号： H01L29/76

CPC分类号： H01L27/127 ,  G11C7/062 ,  H01L27/1214 ,  H03F3/45192 ,  H03F3/45219 ,  H03K5/2481 ,  H03K19/0016

摘要： When n-channel thin film transistors(TFTs) and p-channel TFTs are formed on a polycrystalline silicon film formed on a glass substrate, a process is included in which P-dopant or N-dopant is introduced at the same time to the channel region of a part of the n-channel TFTs and a part of the p-channel TFTs. In one channel doping operation, a set of low-VT and high-VT p-channel TFTs and a set of low-VT and high-VT n-channel TFTs can be formed. This method is used for forming high-VT TFTs, which can reduce the off-current, in logics and switch circuits and for forming low-VT TFTs, which can enlarge the dynamic range, in analog circuits to improve the performance of a thin film semiconductor.

摘要翻译： 当在形成在玻璃基板上的多晶硅膜上形成n沟道薄膜晶体管（TFT）和p沟道TFT时，包括其中P掺杂剂或N掺杂剂同时引入沟道的工艺 n沟道TFT的一部分的区域和p沟道TFT的一部分。 在单通道掺杂操作中，可以形成一组低VT和高VT p沟道TFT以及一组低VT和高VT n沟道TFT。 该方法用于形成高VT TFT，其可以减少逻辑和开关电路中的截止电流，并且用于形成低VT TFT，这可以扩大模拟电路中的动态范围，以提高薄膜的性能 半导体。

公开(公告)号：US20070159248A1

公开(公告)日：2007-07-12

申请号：US11638535

申请日：2006-12-14

申请人： Hiroshi Tsuchi

发明人： Hiroshi Tsuchi

IPC分类号： H03F3/45

CPC分类号： H03F3/45192 ,  H03F3/3022 ,  H03F3/45179 ,  H03F2203/45116 ,  H03F2203/45166 ,  H03F2203/45171 ,  H03F2203/45236 ,  H03F2203/45281 ,  H03F2203/45641

摘要： A differential amplifying circuit capable of reducing amplitude-difference deviation over a full range of grayscale voltages inclusive of voltages in the vicinity of power-supply voltage includes first and second differential pairs of mutually different polarities, in which the outputs of the differential pairs are coupled by a coupling stage. One of the first and second differential pairs receives an input signal from an input terminal and a feedback signal from an output terminal at a pair of inputs thereof, and the other differential pair receives reference signals (which may be of the same voltage), which have voltage levels that set the other differential pair transistors to an on-state, at a pair of inputs of the other differential pair.

摘要翻译： 能够减小包括电源电压附近的电压的全范围灰度级电压的差分偏差的差分放大电路包括相互不同极性的第一和第二差分对，其中差分对的输出耦合 通过耦合阶段。 第一和第二差分对之一接收来自输入端的输入信号和来自其输入端的输出端的反馈信号，另一个差分对接收参考信号（其可以是相同的电压），其中 具有在另一个差分对的一对输入处将另一个差分对晶体管设置为导通状态的电压电平。

公开(公告)号：US20070126689A1

公开(公告)日：2007-06-07

申请号：US11633518

申请日：2006-12-05

申请人： Junichiro Ishii ,  Hiroshi Tsuchi

发明人： Junichiro Ishii ,  Hiroshi Tsuchi

IPC分类号： G09G3/36

CPC分类号： H03M1/0646 ,  G09G3/2011 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2320/0276 ,  H03M1/76

摘要： Disclosed is a digital-to-analog converter including a decoder which receives m (where m>=4 holds) reference voltages having voltage values that differ from one another, and selects and outputs n (where n>=3 holds) identical or different voltages from among the m reference voltages based upon a digital signal; and an amplifying circuit that outputs a voltage, which is obtained by taking the weighted mean of the selected n voltages at a ratio of 2n−1:2n−2: . . . :20, from an output terminal.

摘要翻译： 公开了一种数模转换器，其包括接收m（其中m≥4）的解码器，其具有彼此不同的电压值的参考电压，并且选择并输出n（其中n> = 3成立）相同或不同 基于数字信号的m个参考电压中的电压; 以及放大电路，其输出通过以2比特的比例获取所选择的n个电压的加权平均值而获得的电压：2 2： 。 。 。 ：2 <0> 0 。

公开(公告)号：US07224224B2

公开(公告)日：2007-05-29

申请号：US10657196

申请日：2003-09-09

申请人： Kenji Sera ,  Hiroshi Tsuchi

发明人： Kenji Sera ,  Hiroshi Tsuchi

IPC分类号： H03F3/45

CPC分类号： H01L27/127 ,  G11C7/062 ,  H01L27/1214 ,  H03F3/45192 ,  H03F3/45219 ,  H03K5/2481 ,  H03K19/0016

摘要： When n-channel thin film transistors(TFTs) and p-channel TFTs are formed on a polycrystalline silicon film formed on a glass substrate, a process is included in which P-dopant or N-dopant is introduced at the same time to the channel region of a part of the n-channel TFTs and a part of the p-channel TFTs. In one channel doping operation, a set of low-VT and high-VT p-channel TFTs and a set of low-VT and high-VT n-channel TFTs can be formed. This method is used for forming high-VT TFTs, which can reduce the off-current, in logics and switch circuits and for forming low-VT TFTs, which can enlarge the dynamic range, in analog circuits to improve the performance of a thin film semiconductor.

摘要翻译： 当在形成在玻璃基板上的多晶硅膜上形成n沟道薄膜晶体管（TFT）和p沟道TFT时，包括其中P掺杂剂或N掺杂剂同时引入沟道的工艺 n沟道TFT的一部分的区域和p沟道TFT的一部分。 在单通道掺杂操作中，可以形成一组低VT和高VT p沟道TFT以及一组低VT和高VT n沟道TFT。 该方法用于形成高VT TFT，其可以减少逻辑和开关电路中的截止电流，并且用于形成低VT TFT，这可以扩大模拟电路中的动态范围，以提高薄膜的性能 半导体。