公开(公告)号：US07148550B2

公开(公告)日：2006-12-12

申请号：US10393278

申请日：2003-03-21

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L29/82

CPC分类号： B82Y25/00 ,  G11C11/15 ,  H01F10/3254

摘要： A semiconductor device includes a memory portion in which a plurality of magneto-resistance effect elements each having a hard-axis of magnetization and an easy-axis of magnetization are arranged and one of binary data is written in all the magneto-resistance effect elements, and a circuit portion to which a write current is supplied to write only the other one of the binary data in only a selected magneto-resistance effect element selected from the magneto-resistance effect elements.

摘要翻译： 一种半导体器件包括存储部，其中布置有具有硬磁化强度的轴和容易磁化轴的多个磁阻效应元件，并且将二进制数据中的一个写入所有磁阻效应元件中， 以及电路部分，其中仅供给从电磁效应元件选择的选定的磁阻效应元件中仅供给二进制数据中的另一个的写入电流。

公开(公告)号：US07061032B2

公开(公告)日：2006-06-13

申请号：US10787133

申请日：2004-02-27

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L29/772

CPC分类号： H01L29/7841 ,  H01L21/84 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1203

摘要： A semiconductor device including: a cell transistor including: a pair of source and drain regions formed in a surface portion of a silicon substrate so as to have a predetermined space therebetween; a channel region sandwiched by the source and drain regions; a gate formed above the channel region with a gate dielectric film being formed therebetween; and a silicon plug formed on the silicon substrate, the silicon plug electrically contacting the source and drain regions, an upper portion of the silicon plug being a first self-aligned silicide portion.

摘要翻译： 一种半导体器件，包括：单元晶体管，包括：一对源极和漏极区，形成在硅衬底的表面部分中，以在其间具有预定的间隔; 夹在源区和漏区之间的沟道区; 形成在通道区域上方的栅极，其间形成有栅极电介质膜; 以及形成在所述硅衬底上的硅插头，所述硅插头电接触所述源极和漏极区域，所述硅插头的上部是第一自对准硅化物部分。

公开(公告)号：US20050275000A1

公开(公告)日：2005-12-15

申请号：US10917300

申请日：2004-08-13

申请人： Takeshi Kajiyama ,  Hisanori Aikawa ,  Tomomasa Ueda ,  Tatsuya Kishi ,  Masatoshi Yoshikawa

发明人： Takeshi Kajiyama ,  Hisanori Aikawa ,  Tomomasa Ueda ,  Tatsuya Kishi ,  Masatoshi Yoshikawa

IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L27/22 ,  H01L31/113 ,  H01L43/08

CPC分类号： H01L27/228 ,  B82Y10/00

摘要： A magnetic memory device includes a first write wiring line including a wiring layer formed in a trench in an insulation layer, a barrier metal layer buried in the trench over the wiring layer. And the device includes a magneto-resistance effect element provided on the first write wiring line.

摘要翻译： 磁存储器件包括：第一写入布线，其包括形成在绝缘层中的沟槽中的布线层;掩埋在布线层上的沟槽中的阻挡金属层。 并且该器件包括设置在第一写入布线上的磁阻效应元件。

公开(公告)号：US20050201147A1

公开(公告)日：2005-09-15

申请号：US10847362

申请日：2004-05-18

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L27/105 ,  G11C11/15 ,  H01L21/8246

CPC分类号： H01L27/228 ,  B82Y10/00 ,  H01L43/08 ,  H01L43/12

摘要： A magnetic random access memory according to an aspect of the present invention comprises a first magnetic layer in which a magnetization state is fixed, a second magnetic layer which has a shape different from that of the first magnetic layer and in which a magnetization state varies in accordance with write data, a non-magnetic layer which is arranged between the first magnetic layer and the second magnetic layer, and a third magnetic layer which surrounds the second magnetic layer.

摘要翻译： 根据本发明的一个方面的磁性随机存取存储器包括其中固定有磁化状态的第一磁性层，具有与第一磁性层的形状不同的磁化状态变化的第二磁性层 根据写入数据，布置在第一磁性层和第二磁性层之间的非磁性层和围绕第二磁性层的第三磁性层。

公开(公告)号：US5982008A

公开(公告)日：1999-11-09

申请号：US916428

申请日：1997-08-22

申请人： Takeshi Kajiyama

发明人： Takeshi Kajiyama

IPC分类号： H01L21/76 ,  H01L21/28 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/08 ,  H01L27/108 ,  H01L29/423 ,  H01L29/76

CPC分类号： H01L21/28123 ,  H01L21/76232 ,  H01L29/4238

摘要： In a MOS transistor using shallow trench isolation, a patten of an element formation region has a shape of a modified hexagon in which a hexagon is compressed into a shape like a rhombus in a direction perpendicular to an extension direction of a gate electrode wiring. The pattern of element formation region is constructed as described above, so that an element formation region is formed in a lager current path in a corner device. Thus, a lowering of a threshold voltage (a short channel effect) due to the corner device can be restricted without increasing a width of the gate electrode wiring.

摘要翻译： 在使用浅沟槽隔离的MOS晶体管中，元件形成区域的图案具有改变的六边形的形状，其中六边形沿垂直于栅电极布线的延伸方向的方向被压缩成像菱形的形状。 如上所述构成元件形成区域的图案，使得元件形成区域形成在拐角装置中的较大电流路径中。 因此，可以在不增加栅电极布线的宽度的情况下限制由于拐角装置引起的阈值电压（短沟道效应）的降低。