公开(公告)号：US5969400A

公开(公告)日：1999-10-19

申请号：US614340

申请日：1996-03-12

申请人： Takashi Shinohe ,  Yoshihiro Minami ,  Ichiro Omura

发明人： Takashi Shinohe ,  Yoshihiro Minami ,  Ichiro Omura

IPC分类号： H01L27/07 ,  H01L29/06 ,  H01L29/08 ,  H01L29/739 ,  H01L29/861 ,  H01L23/58

CPC分类号： H01L27/0761 ,  H01L29/0615 ,  H01L29/0834 ,  H01L29/7394 ,  H01L29/7395 ,  H01L29/8611 ,  H01L2924/0002

摘要： A semiconductor device includes a first semiconductor layer of a first conductivity type having first and second main surfaces, a second semiconductor layer of a second conductivity type selectively formed on the first main surface of the first semiconductor layer, the second semiconductor layer including a first region having a relatively high injection efficiency and a second region having a relatively low injection efficiency and the first region being surrounded by the second region, a third semiconductor layer of the first conductivity type formed on the second main surface of the first semiconductor layer, a first electrode selectively formed on the second semiconductor layer of the second conductivity type and connected to at least the first region, and a second electrode formed on the third semiconductor layer of the first conductivity type.

摘要翻译： 半导体器件包括具有第一和第二主表面的第一导电类型的第一半导体层，选择性地形成在第一半导体层的第一主表面上的第二导电类型的第二半导体层，第二半导体层包括第一区域 具有相对较高的注入效率和具有相对低的注入效率的第二区域，并且第一区域被第二区域包围，形成在第一半导体层的第二主表面上的第一导电类型的第三半导体层，第一 电极选择性地形成在第二导电类型的第二半导体层上并连接到至少第一区域，第二电极形成在第一导电类型的第三半导体层上。

公开(公告)号：US5381026A

公开(公告)日：1995-01-10

申请号：US760344

申请日：1991-09-16

申请人： Takashi Shinohe ,  Kazuya Nakayama ,  Minami Takeuchi ,  Masakazu Yamaguchi ,  Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa

发明人： Takashi Shinohe ,  Kazuya Nakayama ,  Minami Takeuchi ,  Masakazu Yamaguchi ,  Mitsuhiko Kitagawa ,  Ichiro Omura ,  Akio Nakagawa

IPC分类号： H01L29/423 ,  H01L29/745 ,  H01L29/749 ,  H01L27/08 ,  H01L29/74

CPC分类号： H01L29/7455 ,  H01L29/42308 ,  H01L29/749

摘要： Disclosed herein is an insulated-gate thyristor comprising a base layer of a first conductivity type, having first and second major surfaces, a first main-electrode region of the first conductivity type, formed in the first major surface of the base layer, a second main-electrode region of a second conductivity type, formed in the second major surface of the base layer, at least a pair of grooves extending from the first main-electrode region into the base layer, and opposing each other and spaced apart by a predetermined distance, insulated gate electrodes formed within the grooves, and a turn-off insulated-gate transistor structure for releasing carriers of the second conductivity type from the base layer.

公开(公告)号：US5210432A

公开(公告)日：1993-05-11

申请号：US615252

申请日：1990-11-19

申请人： Takashi Shinohe ,  Masaki Atsuta ,  Akio Nakagawa

发明人： Takashi Shinohe ,  Masaki Atsuta ,  Akio Nakagawa

IPC分类号： H01L29/744 ,  H01L29/08 ,  H01L29/74 ,  H01L29/749

CPC分类号： H01L29/0839

摘要： According to this invention, there is disclosed an insulated gate GTO thyristor comprising a pnpn structure including a p-type emitter layer, an n-type base layer, a p-type base layer, and an n-type emitter layer. The thyristor has a first gate electrode contacting the p-type base layer and a second gate electrode formed on a channel region of the p-type base layer through a gate insulating film. An n+-type layer of the n-type emitter layer immediately below a cathode electrode and an n--type layer of the n-type emitter layer contacting the channel region are formed in different manufacturing steps, and an emitter breakdown voltage and the threshold voltage of the second gate electrode are optimally set.

摘要翻译： 根据本发明，公开了一种包括p型结构的绝缘栅GTO晶闸管，其包括p型发射极层，n型基极层，p型基极层和n型发射极层。 晶闸管具有通过栅极绝缘膜与p型基极层接触的第一栅电极和形成在p型基极层的沟道区上的第二栅电极。 在不同的制造步骤中形成正好在阴极电极正下方的n型发射极层的n +型层和与沟道区接触的n型发射极层的n型层，并且发射极击穿电压和阈值 最优地设定第二栅电极的电压。

公开(公告)号：US4914496A

公开(公告)日：1990-04-03

申请号：US157584

申请日：1988-02-19

申请人： Akio Nakagawa ,  Takashi Shinohe

发明人： Akio Nakagawa ,  Takashi Shinohe

IPC分类号： H01L29/74 ,  H01L29/745 ,  H01L29/749

CPC分类号： H01L29/7455 ,  H01L29/7428 ,  H01L29/749

摘要： A gate turn-off thyristor has first and second MOSFETs serving as turn-on and turn-off controlling devices, respectively. A p type semiconductor layer is additionally formed in an n type substrate functioning as a first base in such a manner as to overlap a p type second base layer. The additional layer is different from the second base in impurity concentration, thereby causing the resistivity of the second base to be smaller than that of the additional layer. The first MOSFET has an n type source layer formed in the additional layer to define a surface portion of the additional layer positioned between the source layer and the first base layer as a channel region of the first MOSFET. A turn-on gate layer is provided to cover a surface region of the first base and the channel region of the first MOSFET.

公开(公告)号：US4617583A

公开(公告)日：1986-10-14

申请号：US671197

申请日：1984-11-14

申请人： Takashi Shinohe ,  Masayuki Asaka

发明人： Takashi Shinohe ,  Masayuki Asaka

IPC分类号： H01L29/74 ,  H01L29/08 ,  H01L29/744

CPC分类号： H01L29/744 ,  H01L29/0834

摘要： A gate turn-off thyristor has a first emitter layer having a P.sup.+ P.sup.- emitter structure which is in contact with an anode electrode and a second emitter layer having an N-type multi-emitter structure which is in contact with cathode electrodes. To reduce power dissipation in the turn-off process, the first emitter layer mainly consists of low impurity concentration regions, and each high impurity concentration region is formed to have a substantially uniform width and to surround the low impurity concentration region formed within a region of the first emitter layer immediately below one of the emitter strips of the second emitter layer.

摘要翻译： 栅极截止晶闸管具有与阳极接触的具有P + P-发射极结构的第一发射极层和具有与阴极接触的N型多发射极结构的第二发射极层。 为了减少关断过程中的功率消耗，第一发射极层主要由低杂质浓度区组成，并且每个高杂质浓度区形成为具有基本均匀的宽度并且围绕形成在 位于第二发射极层的发射极条之一之下的第一发射极层。