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公开(公告)号：US20070216467A1
公开(公告)日：2007-09-20
申请号：US11717717
申请日：2007-03-14
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
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公开(公告)号：US20070183214A1
公开(公告)日：2007-08-09
申请号：US11703672
申请日：2007-02-08
CPC分类号： G11C29/48 , G11C29/12 , G11C29/12005
摘要： A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data and a power supply circuit portion supplying a first voltage and a second voltage to the memory portion. The memory portion writes or reads data to or from the memory cells based on the first voltage and the second voltage, and the power supply circuit portion provides a smaller voltage difference between the first voltage and the second voltage in the second operation mode as compared with the voltage difference in the first operation mode.
摘要翻译： 半导体器件具有第一操作模式和第二操作模式，其中提供具有比第一操作模式中更高的电压值的电源。 半导体器件包括具有用于存储数据的存储单元的存储器部分和向存储器部分提供第一电压和第二电压的电源电路部分。 存储器部分基于第一电压和第二电压将数据写入或从存储器单元读取数据，并且电源电路部分在第二操作模式中在第一电压和第二电压之间提供较小的电压差，与第 在第一操作模式下的电压差。
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公开(公告)号：US06965148B2
公开(公告)日：2005-11-15
申请号：US10224317
申请日：2002-08-21
申请人： Masakazu Hirose , Fukashi Morishita
发明人： Masakazu Hirose , Fukashi Morishita
IPC分类号： H01L21/8242 , H01L21/84 , H01L27/108 , H01L27/12 , H01L29/786 , H01L31/0312
CPC分类号： H01L27/10873 , G11C11/404 , G11C11/4085 , G11C2211/4016 , H01L21/84 , H01L27/0218 , H01L27/10808 , H01L27/10817 , H01L27/10832 , H01L27/10835 , H01L27/10882 , H01L27/10894 , H01L27/1203 , H01L29/78612
摘要： In this semiconductor memory device, a potential clamping region having no insulation layer formed therein is provided in an insulation layer. More specifically, the potential clamping region is formed under a body portion at a position near a first impurity region, and extends to a first semiconductor layer. A body fixing portion is formed in a boundary region between the body portion and the potential clamping region. This structure enables improvement in operation performance without increasing the layout area in the case where a DRAM cell is formed in a SOI (Silicon On Insulator) structure.
摘要翻译： 在该半导体存储器件中，在绝缘层中设置不形成有绝缘层的电位钳位区域。 更具体地，电位钳位区域形成在靠近第一杂质区域的位置的主体部分下方，并延伸到第一半导体层。 主体固定部分形成在主体部分和电位夹紧区域之间的边界区域中。 在SOI（绝缘体上硅）结构中形成DRAM单元的情况下，这种结构能够提高操作性能而不增加布局面积。
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94.发明授权Potential detecting circuit having wide operating margin and semiconductor device including the same 失效包括电位检测电路的半导体装置具有宽的工作裕度公开(公告)号：US06614270B2
公开(公告)日：2003-09-02
申请号：US09809212
申请日：2001-03-16
申请人： Mako Okamoto , Yasuhiko Taito , Fukashi Morishita , Akira Yamazaki , Mihoko Akiyama , Nobuyuki Fujii
发明人： Mako Okamoto , Yasuhiko Taito , Fukashi Morishita , Akira Yamazaki , Mihoko Akiyama , Nobuyuki Fujii
IPC分类号： H03K522
CPC分类号： G11C5/145 , G11C11/4074 , H02M3/073
摘要： In a detector included in a VPP generating circuit in a DRAM, an external power supply potential is applied to the gate of an N-channel MOS transistor for regulating a through current of an inverter for outputting an inversion signal of an output signal of a comparator. Since a drain-source voltage of the N-channel MOS transistor can be set to be lower than a threshold voltage Vthn of the N-channel MOS transistor, an operation margin of the detector under conditions of a low voltage and a low temperature is made wider as compared with a conventional technique.
摘要翻译： 在包含在DRAM中的VPP生成电路中的检测器中，外部电源电位被施加到N沟道MOS晶体管的栅极，用于调节反相器的通过电流，以输出比较器的输出信号的反相信号 。 由于N沟道MOS晶体管的漏极 - 源极电压可以被设置为低于N沟道MOS晶体管的阈值电压Vthn，因此在低电压和低温条件下检测器的操作余量 与传统技术相比更宽。
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95.发明授权Semiconductor integrated circuit device having an internal voltage generation circuit layout easily adaptable to change in specification 失效具有容易适应规格变化的内部电压发生电路布局的半导体集成电路器件公开(公告)号：US06519191B1
公开(公告)日：2003-02-11
申请号：US09696011
申请日：2000-10-26
申请人： Fukashi Morishita
发明人： Fukashi Morishita
IPC分类号： G11C700
摘要： An active down converting supplying a large current consumed when a memory array is active, and a Vpp pump for generating a boosted voltage are configured into active units as cells. A required number of active units are provided depending on the array structure and the operation conditions. A power supply circuit can be redesigned and/or rearranged within a short period for adaptation to change in internal structure for the memory array.
摘要翻译： 当存储器阵列处于活动状态时，提供消耗的大电流的有效下变频器和用于产生升压电压的Vpp泵被配置为有源单元作为单元。 根据阵列结构和操作条件，提供所需数量的有效单元。 电源电路可以在短时间内重新设计和/或重新布置，以适应存储器阵列的内部结构的改变。
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公开(公告)号：US06373763B1
公开(公告)日：2002-04-16
申请号：US09839403
申请日：2001-04-23
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C11/4074 , G11C11/4085 , G11C11/4094
摘要： An equalizing circuit includes a plurality of N-channel MOS transistors for respectively setting a data line to a predetermined precharge voltage. The H-level voltage Vddb of a control signal for turning on these N-channel MOS transistors is set to a range higher than the sum of the precharge voltage and a transistor threshold voltage. A Vddb generation circuit steps up an external power-supply voltage and sets a voltage Vddb in a range lower than a step-up voltage for activating a word line.
摘要翻译： 均衡电路包括用于分别将数据线设置为预定预充电电压的多个N沟道MOS晶体管。 用于接通这些N沟道MOS晶体管的控制信号的H电平电压Vddb被设置为高于预充电电压和晶体管阈值电压之和的范围。 Vddb生成电路升高外部电源电压，并将电压Vddb设置在低于用于激活字线的升压电压的范围内。
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公开(公告)号：US06184744B2
公开(公告)日：2001-02-06
申请号：US09149079
申请日：1998-09-08
申请人： Fukashi Morishita
发明人： Fukashi Morishita
IPC分类号： G05F110
CPC分类号： G05F1/465
摘要： An internal power supply voltage generation circuit includes a main amplifier that supplies a current from an external power supply node to an internal power supply line in accordance with the difference between a reference voltage from a reference voltage generation circuit and an internal power supply voltage on the internal power supply line. The current supply amount by the main amplifier is adjusted by a level adjust circuit, according to the difference between the external power supply voltage and the reference voltage. The internal power supply voltage generation circuit can suppress reduction in the internal power supply voltage in the vicinity of the lower limit area of the differential power supply voltage.
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公开(公告)号：US08014224B2
公开(公告)日：2011-09-06
申请号：US12201024
申请日：2008-08-29
申请人： Kenji Yoshinaga , Fukashi Morishita
发明人： Kenji Yoshinaga , Fukashi Morishita
IPC分类号： G11C5/14
CPC分类号： G11C5/147
摘要： There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by an internal buck voltage. On the other hand, a data path with high power consumption is driven by an external power supply voltage. A level conversion circuit receives an address signal or a command signal having a voltage level of the external power supply voltage, converts the voltage level to the internal buck voltage, and outputs a resultant signal to the control circuit. A level conversion circuit receives a control signal having a voltage level of the internal buck voltage from the control circuit, converts the voltage level to the external power supply voltage, and outputs a resultant signal to the data path.
摘要翻译： 提供了由内部发电电路产生的内部电力提供的半导体器件，以执行稳定的操作，并且还抑制功耗。 控制电路，行/列解码器和读出放大器由内部降压电压驱动。 另一方面，具有高功耗的数据路径由外部电源电压驱动。 电平转换电路接收具有外部电源电压的电压电平的地址信号或指令信号，将电压电平转换为内部降压电压，并将结果信号输出到控制电路。 电平转换电路从控制电路接收具有内部降压电压的电压电平的控制信号，将电压电平转换为外部电源电压，并将结果信号输出到数据路径。
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公开(公告)号：US20110182131A1
公开(公告)日：2011-07-28
申请号：US13080114
申请日：2011-04-05
IPC分类号： G11C5/14
摘要： A semiconductor integrated circuit device has a negative voltage generation circuit provided at each power supply circuit unit for six memory macros. Therefore, the response with respect to variation in a negative voltage is increased. In a standby mode, a negative voltage supply line for the six memory macros is connected by a switch circuit, and only a negative voltage generation circuit of one power supply circuit unit among six negative voltage generation circuits of the six power supply circuit units is rendered active. Thus, increase in standby current can be prevented.
摘要翻译： 半导体集成电路器件具有设置在每个用于六个存储器宏的电源电路单元的负电压产生电路。 因此，相对于负电压的变化的响应增加。 在待机模式下，通过开关电路连接六个存储器宏的负电压供给线，并且仅在六个电源电路单元的六个负电压产生电路中仅一个电源电路单元的负电压产生电路 活性。 因此，可以防止待机电流的增加。
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公开(公告)号：US20100231768A1
公开(公告)日：2010-09-16
申请号：US12722121
申请日：2010-03-11
IPC分类号： H04N5/335
CPC分类号： H04N5/37455 , H03M1/1205 , H03M1/144 , H03M1/403 , H03M1/66 , H03M2201/16 , H04N5/374 , H04N5/3742 , H04N5/3765 , H04N5/378
摘要： There is provided a solid-state image pickup device including ADCs that can be arranged in a limited space. The potential of a pixel signal outputted through a vertical readout line is held at a node. A plurality of capacitors are capacitively coupled to the node at which the pixel signal is held. The potential of the node is decreased in a stepwise manner by sequentially switching the voltages of the counter electrodes of the capacitors by the control of transistors. A comparator compares the potential of the node with the potential of the dark state of the pixel, and determines the upper bits of a digital value when the potential of the node becomes lower than the potential of the dark state. Following this, the conversion of the lower bits of the digital value is started. Therefore, it is possible to simplify the configuration of each ADC and arrange each ADC in a limited space.
摘要翻译： 提供了包括可以在有限空间中布置的ADC的固态图像拾取装置。 通过垂直读出线输出的像素信号的电位被保持在节点处。 多个电容器电容耦合到保持像素信号的节点。 通过晶体管的控制，通过依次切换电容器对置电极的电压，逐步降低节点的电位。 比较器将节点的电位与像素的暗状态的电位进行比较，并且当节点的电位变得低于黑暗状态的电位时，确定数字值的高位。 此后，开始数字值的低位的转换。 因此，可以简化每个ADC的配置，并将每个ADC排列在有限的空间内。
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