公开(公告)号：US5548744A

公开(公告)日：1996-08-20

申请号：US354934

申请日：1994-12-12

申请人： Toshihiko Ogura ,  Hiroaki Aotsu ,  Koichi Kimura ,  Hiromichi Enomoto ,  Tadashi Kyoda

发明人： Toshihiko Ogura ,  Hiroaki Aotsu ,  Koichi Kimura ,  Hiromichi Enomoto ,  Tadashi Kyoda

IPC分类号： G09G5/393 ,  G06F12/00

CPC分类号： G09G5/393 ,  G09G2340/10

摘要： In a memory circuit having a memory device operative to read, write and hold data and an operation unit implementing computation between a first datum supplied externally and a second datum read out of the memory device, a selector for selecting one of operational function specification data preset externally and a selector for selecting one of bit write control data present externally are given with select control signals, so that a frame buffer memory operative in read-modify-write mode can be used commonly.

摘要翻译： 在具有可操作以读取，写入和保持数据的存储器件的存储器电路以及在从外部提供的第一数据和从存储器件读出的第二数据之间实现计算的操作单元中选择一个操作功能指定数据预设 外部选择器和用于选择外部存在的位写控制数据中的一个的选择器给出选择控制信号，使得可以通常使用以读 - 修改 - 写模式操作的帧缓冲存储器。

公开(公告)号：US5493528A

公开(公告)日：1996-02-20

申请号：US435959

申请日：1995-05-05

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G11C13/00

CPC分类号： G06T1/20 ,  G06F7/575 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

公开(公告)号：US5462442A

公开(公告)日：1995-10-31

申请号：US197841

申请日：1994-02-17

申请人： Masaya Umemura ,  Toshihiko Ogura ,  Hideki Osaka ,  Masatsugu Shinozaki

发明人： Masaya Umemura ,  Toshihiko Ogura ,  Hideki Osaka ,  Masatsugu Shinozaki

IPC分类号： H01R24/00 ,  H01R31/06 ,  H05K1/14 ,  H05K7/14 ,  H05K1/00

CPC分类号： H01R23/68 ,  H05K1/144 ,  H05K7/1441 ,  H01R12/722

摘要： In a connector having a plurality of first contact groups arranged in a predetermined pattern, conductors whose one ends are connected to the first contact groups, and a plurality of second contact groups arranged in a pattern corresponding to the pattern of the first contact groups, the conductors for connecting the first contact groups and the second contact groups cause portions of the first contact groups to be connected to the second contact groups at different positions within the above-described pattern. Accordingly, even when the contacts of the same sort of signal lines having one-to-one correspondence are allocated to the contact conductors located at the same positions within the boards for constituting the respective modules, the one-to-one correspondence can be maintained, and thus the printed-circuit boards of the modules can be commonly utilized.

摘要翻译： 在具有以预定图案布置的多个第一接触组的连接器中，其一端连接到第一接触组的导体和以与第一接触组的图案对应的图案布置的多个第二接触组， 用于连接第一接触组和第二接触组的导体使得第一接触组的部分在上述图案中的不同位置处连接到第二接触组。 因此，即使将具有一一对应的相同种类的信号线的触点分配给位于用于构成各个模块的板内的相同位置的接触导体，也可以保持一一对应 ，因此可以通常使用模块的印刷电路板。

公开(公告)号：US5448519A

公开(公告)日：1995-09-05

申请号：US294407

申请日：1994-08-23

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara ,  Hiromichi Enomoto ,  Tadashi Kyoda

IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G11C13/00

CPC分类号： G06T1/20 ,  G06F7/575 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

摘要： A memory device formed on an IC chip includes dynamic random access memories for effecting data read and write operations, first and second data terminals for receiving data from an external side of the IC chip, and a controller having a first data input connected to the first data terminal to receive first data, a second input connected to receive second data read, a third data input connected to the second data terminal to receive a function mode signal, and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input. The operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data. The second data is read out of a selected part of the storage locations. The operation corresponding to the function set by the function setting unit is executed for the first and second data. The result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle.

公开(公告)号：USRE34635E

公开(公告)日：1994-06-07

申请号：US988311

申请日：1992-12-09

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Kiichiro Urabe

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Kiichiro Urabe

IPC分类号： G06F7/00 ,  G06F3/153 ,  G06F9/308 ,  G06F9/20

CPC分类号： G06F9/30018

摘要： A bit operation processor having a first address operation unit for updating the address of data in units of a byte or multiple bytes for performing operation in units of a byte or multiple bytes. A second address operation unit for updating the address of data in units of a bit or multiple bits, an address controller operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit. Fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.

摘要翻译： 一种位操作处理器，具有第一地址操作单元，用于以字节或多字节为单位更新数据的地址，以便以字节或多个字节为单位进行操作。 第二地址操作单元，用于以比特或多个比特为单位更新数据的地址;操作在第一地址操作单元上的地址控制器，以响应于第二地址操作单元的地址提前结果来推进地址。 获取由第一地址操作单元寻址的操作的字节宽数据，从而简单且快速地控制字节块中任何位置处的任何位数的数据之间的操作。

公开(公告)号：US5265204A

公开(公告)日：1993-11-23

申请号：US836738

申请日：1992-02-19

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Kiichiro Urabe

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Kiichiro Urabe

IPC分类号： G06F9/308 ,  G06F15/20

CPC分类号： G06F9/30018

摘要： A bit operation processor having a first address operation unit for updating the address of data in units of byte or multipled bytes for performing operation in units of byte or multiple of bytes, a second address operation unit for updating the address of data in units of bit or multiple of bits, an address control means operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit, and means for fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.

摘要翻译： 一种位操作处理器，具有第一地址操作单元，用于以字节或乘法字节为单位更新数据地址，以字节或多字节为单位进行操作;第二地址操作单元，用于以位为单位更新数据的地址 或多个位，响应于第二地址操作单元的地址提前结果而在第一地址操作单元上操作以提前地址的地址控制装置，以及用于获取由第一地址操作单元寻址的操作的字节宽数据的装置 地址操作单元，从而简单且快速地控制字节块中任何位置处的任何位数的数据之间的操作。

公开(公告)号：US5175838A

公开(公告)日：1992-12-29

申请号：US349403

申请日：1989-05-08

申请人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara

发明人： Koichi Kimura ,  Toshihiko Ogura ,  Hiroaki Aotsu ,  Mitsuru Ikegami ,  Tadashi Kuwabara

IPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393

CPC分类号： G06F7/575 ,  G06T1/20 ,  G06T1/60 ,  G09G5/393 ,  G09G2340/10

摘要： A memory circuit including memory elements on which the data read, write, and store operations can be arbitrarily performed, the memory elements having a dyadic/arithmetic operation function. In a read/modify/write mode to be executed during a memory cycle and in an interval in which data from the memory elements and data from external devices exist, an operation is executed between the external data and the data in the memory elements and the operation result is stored during a write cycle, thereby achieving a higher-speed operation.

摘要翻译： 包括可以任意执行数据读取，写入和存储操作的存储器元件的存储器电路，存储元件具有二进制/算术运算功能。 在要在存储器周期中执行的读取/修改/写入模式中，并且存储来自存储器元件的数据和来自外部设备的数据的间隔中，在外部数据和存储器元件中的数据之间执行操作， 在写入周期期间存储操作结果，从而实现更高速的操作。

公开(公告)号：US4872131A

公开(公告)日：1989-10-03

申请号：US192547

申请日：1988-05-11

申请人： Kazumi Kubota ,  Kazushi Kobayashi ,  Toshihiko Ogura

发明人： Kazumi Kubota ,  Kazushi Kobayashi ,  Toshihiko Ogura

IPC分类号： G06F7/00 ,  G06F7/50 ,  G06F7/507 ,  G06F7/57 ,  G06F7/76

CPC分类号： G06F7/57 ,  G06F2207/3828

摘要： Two arithmetic logic units (ALUs) are provided, one a high-order side and another on a low-order side such that data on the high-order side and on low-order side, output from each of a source data register and a destination data register, are respectively supplied to the ALUs to be operated on thereby. There is provided a selector circuit on the output side of the source data register, which selector circuit operates to deliver the data on the high-order side and that on the low-order side from the source data register selectively to the ALU on the high-order side and that on the low-order side according to the operating mode. Carry outputs from each of the ALUs are input to a first selector and one is selected according to the operating mode and stored in a carry flag register. The output of the carry flag register and the carry output of the ALU on the low-order side are input to a second selector whereby one output thereof is selected according to the operating mode and input to the ALU on the high-order side as the carry input thereto, and also, the output of the carry flag register is supplied to the ALU on the low-order side as the carry input thereto.

摘要翻译： 提供两个算术逻辑单元（ALU），一个位于高阶侧，另一个位于低位侧，使得从源数据寄存器和源数据寄存器中的每一个输出的高阶侧和低位侧的数据 目的地数据寄存器分别提供给要操作的ALU。 在源数据寄存器的输出侧提供选择器电路，该选择器电路用于将高数据侧的数据和从源数据寄存器的低阶侧的数据选择性地传送到ALU的高位 - 根据操作模式在低端侧。 将来自每个ALU的输出输入到第一选择器，并根据操作模式选择一个并存储在进位标志寄存器中。 进位标志寄存器的输出和低位侧的ALU的进位输出被输入到第二选择器，由此根据操作模式选择其一个输出，并将其输入到高阶侧的ALU作为 进位输入，并且进位标志寄存器的输出也作为进位输入提供给低位侧的ALU。

公开(公告)号：US4757473A

公开(公告)日：1988-07-12

申请号：US865376

申请日：1986-05-21

申请人： Ryoichi Kurihara ,  Hiroaki Aotsu ,  Toshihiko Ogura ,  Koichi Kimura ,  Tadashi Kyoda ,  Hiromichi Enomoto

发明人： Ryoichi Kurihara ,  Hiroaki Aotsu ,  Toshihiko Ogura ,  Koichi Kimura ,  Tadashi Kyoda ,  Hiromichi Enomoto

IPC分类号： G06F12/06 ,  G06F12/04 ,  G11C7/10 ,  G11C8/16 ,  G11C11/34 ,  G11C7/00

CPC分类号： G11C7/1075 ,  G11C8/16

摘要： A dual-port memory circuit comprises a random port having a memory cell array randomly accessable and a serial port serially readable or writable from/to the memory cell array. In the memory circuit, two modes are provided to the serial port, and when a first mode is designated, the data are consecutively read or written a plurality of bits at a time, and when a second mode is designated, the data are consecutively read or written one bit at a time. High speed read/write operation is attained by designating the mode to allow parallel input/output. For an application which does not require high speed operation, the number of components to be externally added to the memory circuit can be reduced.

摘要翻译： 双端口存储器电路包括具有随机存取的存储单元阵列的随机端口和从存储单元阵列串行读取或写入的串行端口。 在存储器电路中，向串行端口提供两种模式，并且当指定第一模式时，一次连续地读取或写入多个位，并且当指定第二模式时，连续读取数据 或一次写一位。 通过指定允许并行输入/输出的模式可以实现高速读/写操作。 对于不需要高速操作的应用，可以减少外部添加到存储器电路的组件的数量。

公开(公告)号：US08891728B2

公开(公告)日：2014-11-18

申请号：US13581141

申请日：2011-02-23

申请人： Toshihiko Ogura

发明人： Toshihiko Ogura

IPC分类号： G21K7/00 ,  G01N23/225

CPC分类号： G21K7/00 ,  G01N23/2251 ,  H01J2237/20 ,  H01J2237/2445 ,  H01J2237/28

摘要： A specimen supporting member (10) includes: a specimen supporting film (11) such as a silicon nitride film, a carbon film, and a polyimide film; an X-ray radiation film (13) provided on one principal surface of the specimen supporting film, and for radiating a characteristic X-ray in a soft X-ray region upon irradiation with charged particles; and a specimen adsorption film (12) which is a metal film provided on another principal surface of the specimen supporting film (11), and which fixes by adsorption a specimen (1) to be observed. Since a protein which is a constitutive substance of a biological specimen has a characteristic to easily adsorb to a metallic ion, a specimen adsorption film (12) is formed on one principal surface of the specimen supporting film (11) so that an observation specimen adsorbs thereto.

摘要翻译： 样品支撑构件（10）包括：诸如氮化硅膜，碳膜和聚酰亚胺膜的样品支撑膜（11）; 设置在试样支撑膜的一个主面上的X射线辐射膜（13），用于在带电粒子照射时在软X射线区域照射特征X射线; 以及作为在试样支撑膜（11）的另一主面上设置的金属膜的试样吸附膜（12），通过吸附待观察的试样（1）固定。 由于作为生物样品的组成物质的蛋白质具有容易吸附到金属离子的特性，因此在试样支撑膜（11）的一个主面上形成试样吸附膜（12），使得观察试样吸附 到此。