公开(公告)号：US07290074B2

公开(公告)日：2007-10-30

申请号：US11100081

申请日：2005-04-06

申请人： Shigehiro Asano ,  Tsutomu Ishli

发明人： Shigehiro Asano ,  Tsutomu Ishli

IPC分类号： G06F13/00

CPC分类号： G06F13/4009

摘要： Systems and methods for implementing back-off timing for retries of commands sent from a master device to a slave device over a split-transaction bus. One embodiment includes a buffer having entries for storing each pending command and associated information, including a number of retries of the command and a static pseudorandom timer expiration value. The timer expiration value of each entry is compared to a running counter according to a mask associated with the number of retries of the command corresponding to the entry. When the unmasked bits of the two values match, the command is retried. In one embodiment, the same portion of the buffer entry that is used to store the number of retries and the timer expiration value is alternately used to store a slave-generated tag that is received with an acknowledgment response.

摘要翻译： 用于通过分割事务总线实现从主设备发送到从设备的命令重试的退避时序的系统和方法。 一个实施例包括具有用于存储每个未决命令和相关信息的条目的缓冲器，包括命令的重试次数和静态伪随机定时器到期值。 根据与对应于条目的命令的重试次数相关联的掩码，将每个条目的定时器到期值与运行计数器进行比较。 当两个值的未屏蔽位匹配时，将重试该命令。 在一个实施例中，用于存储重试次数和定时器到期值的缓冲器条目的相同部分交替地用于存储用确认响应接收的从生产标签。

公开(公告)号：US20070078120A1

公开(公告)日：2007-04-05

申请号：US10576581

申请日：2004-10-19

申请人： Hitoshi Ban ,  Satoshi Ohnuma ,  Norie Tsuboya ,  Shigehiro Asano

发明人： Hitoshi Ban ,  Satoshi Ohnuma ,  Norie Tsuboya ,  Shigehiro Asano

IPC分类号： A61K31/4439 ,  A61K31/4545 ,  A61K31/397

CPC分类号： C07D295/155 ,  C07C309/46 ,  C07C311/21 ,  C07C317/36 ,  C07C323/36 ,  C07C2601/14 ,  C07D211/22 ,  C07D211/26 ,  C07D211/64 ,  C07D223/04 ,  C07D223/06 ,  C07D401/12

摘要： The invention provides a compound of the following formula (1): wherein m, n, and p are independently an integer of 0-4, provided 3≦m+n≦8; X is nitrogen atom or a group of the formula: C—R15; Y is a substituted or unsubstituted aromatic group, etc.; R15, R1, R2, R3, R4, R5, R6 and R7 are hydrogen atom, a substituted or unsubstituted alkyl group, etc.; and Z is hydrogen atom, cyano group, etc., or a prodrug thereof, or a pharmaceutically acceptable salt thereof, which exhibits an action for enhancing LDL receptor expression, and is useful as a medicament for treating hyperlipidemia, atherosclerosis, etc.

摘要翻译： 本发明提供下式（1）的化合物：其中m，n和p独立地为0-4的整数，条件是3 <= m + n <= 8; X是氮原子或下式的基团：C-R 15; Y是取代或未取代的芳基等; R 15，R 1，R 2，R 3，R 4， R 5，R 6和R 7是氢原子，取代或未取代的烷基等; Z为氢原子，氰基等，或其前体药物或其药学上可接受的盐，其具有增强LDL受体表达的作用，可用作治疗高脂血症，动脉粥样硬化等的药物。

公开(公告)号：US20060236008A1

公开(公告)日：2006-10-19

申请号：US11106791

申请日：2005-04-15

申请人： Shigehiro Asano ,  Tsutomu Ishii

发明人： Shigehiro Asano ,  Tsutomu Ishii

IPC分类号： G06F13/00

CPC分类号： G06F13/42

摘要： Systems and methods for facilitating the location of entries in a buffer where a slave device stores information related to an active transaction so that the entries can be removed if the corresponding transactions are canceled. In one embodiment, multiple master devices and multiple slave devices are coupled to a split transaction bus. When a read command is received by a target slave device, the slave device generates an acknowledgment if the slave's command buffer has available entries, or a retry reply if the slave's command buffer is full. The acknowledgment includes a tag which is an index to the buffer location in which the command is stored. If a combined response to the command which is received by the slave device is a retry, the tag, which is included therein, is used by the slave to clear the command from its command buffer.

摘要翻译： 用于促进在缓冲器中的条目的位置的系统和方法，其中从设备存储与活动事务相关的信息，使得如果对应的事务被取消，则可以移除条目。 在一个实施例中，多个主设备和多个从设备耦合到分离事务总线。 当目标从设备接收到读命令时，如果从站的命令缓冲区有可用条目，则从站设备生成一个确认，或者如果从站的命令缓冲区已满，则重试应答。 该确认包括作为其中存储命令的缓冲器位置的索引的标签。 如果对由从设备接收到的命令的组合响应是重试，则被包括在其中的标签被从机用来从其命令缓冲器中清除该命令。

公开(公告)号：US20060190647A1

公开(公告)日：2006-08-24

申请号：US11063174

申请日：2005-02-22

申请人： Shigehiro Asano ,  Tsutomu Ishii

发明人： Shigehiro Asano ,  Tsutomu Ishii

IPC分类号： G06F13/00

CPC分类号： G06F13/4221

摘要： Systems and methods for enabling a slave device to generate a tag that is an index into a buffer where the slave device stores information related to an active transaction such as a write command received by a master device. The tag is sent to the master device with a reply (such as a response to a write command received from the master device), the master device returns the tag with the data to be written to the slave device. The slave device can efficiently associate the received data with the previously sent write command by retrieving the command from the buffer using the tag as an index into the buffer. Additional hardware such as a content-addressable memory unit is not required to make the association.

摘要翻译： 用于使从设备能够生成作为缓存器的索引的标签的系统和方法，其中从设备存储与主设备接收的诸如写命令之类的活动事务相关的信息。 标签通过回复（例如对从主设备接收到的写命令的响应）发送到主设备，主设备将具有要写入从设备的数据的标签返回。 从设备可以通过使用标签作为缓冲器的索引从缓冲器中检索命令来有效地将接收到的数据与先前发送的写入命令相关联。 不需要诸如内容寻址存储器单元的附加硬件来进行关联。

公开(公告)号：US20050165987A1

公开(公告)日：2005-07-28

申请号：US10764626

申请日：2004-01-26

申请人： Shigehiro Asano ,  Peichun Liu ,  David Mui

发明人： Shigehiro Asano ,  Peichun Liu ,  David Mui

IPC分类号： G06F13/362 ,  G06F13/14 ,  G06F13/36

CPC分类号： G06F13/3625

摘要： Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.

摘要翻译： 用于控制一组代理对资源的访问的系统和方法，其中代理具有与其相关联的相应优先级，以及与资源控制相关联的监视器，以及由代理基于优先级访问资源的位置。 一个实施例在具有连接到处理器总线的多个处理器的计算机系统中实现。 处理器总线包括整形监视器，其被配置为控制处理器对总线的访问。 整形监视器根据分配给处理器的优先级，尝试在整个基期内分配来自每个处理器的访问。 整形监视器根据其相对优先级向处理器分配插槽。 首先根据处理器的各自的带宽需求分配优先级，但是可以基于对总线的实际访问和期望访问的比较来修改优先级。

公开(公告)号：US06820187B2

公开(公告)日：2004-11-16

申请号：US09989028

申请日：2001-11-21

申请人： Shigehiro Asano ,  Mitsuo Saito

发明人： Shigehiro Asano ,  Mitsuo Saito

IPC分类号： G06F15163

CPC分类号： G06F13/28

摘要： A multiprocessor system including a master processor, a plurality of processor elements, each of which is provided with a local memory, the processor elements being controlled in accordance with commands from the foregoing master processor, and a global memory shared by the plurality of processor elements is disclosed. The processor elements are provided with a command pooling buffer capable of accumulating a plurality of commands, respectively. DMA controllers are also provided with a command pooling buffer capable of accumulating a plurality of commands, respectively. The master processor persistently issues a plurality of commands to the DMA controller and each processor element. A counter array manages the number of the issued commands which have received no response. When the responses are returned with respect to all issued commands, the counter array notifies the master processor of this.

摘要翻译： 一种多处理器系统，包括主处理器，多个处理器元件，每个处理器元件具有本地存储器，处理器元件根据来自前述主处理器的命令进行控制，以及由多个处理器元件共享的全局存储器 被披露。 处理器元件设置有分别能够累积多个命令的命令池缓冲器。 DMA控制器还具有能分别累积多个命令的命令池缓冲器。 主处理器持续向DMA控制器和每个处理器元件发出多个命令。 计数器阵列管理没有响应的已发出命令的数量。 当相对于所有发出的命令返回响应时，计数器阵列通知主处理器。

公开(公告)号：US06809734B2

公开(公告)日：2004-10-26

申请号：US09815558

申请日：2001-03-22

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki ,  Charles Ray Johns ,  Shigehiro Asano ,  Atsushi Kunimatsu ,  Yukio Watanabe

IPC分类号： G06T120

CPC分类号： G06F9/4893 ,  A63F2300/20 ,  A63F2300/538 ,  Y02D10/24

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network. A system and method for creating a dedicated pipeline for processing streaming data also are provided.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 提供了一种硬件沙盒结构，用于防止由处理单元处理的程序中的数据损坏的安全性。 统一软件单元包含数据和应用程序，并且被构造为由网络的任何处理器进行处理。 每个软件单元在网络上唯一标识。 还提供了一种用于创建用于处理流数据的专用流水线的系统和方法。

公开(公告)号：US06735681B2

公开(公告)日：2004-05-11

申请号：US09794063

申请日：2001-02-28

申请人： Shigehiro Asano ,  Takashi Yoshikawa

发明人： Shigehiro Asano ,  Takashi Yoshikawa

IPC分类号： G06F1200

CPC分类号： G06F9/382 ,  G06F9/3846 ,  G06F9/3848

摘要： A next address computing section contains a selector and is connected to an instruction cache. The instruction cache maintains a predecode result of a branch instruction or predefined settings for a field in this branch instruction. Based on this information maintained in the instruction cache, the selector determines whether the compiler performed a branch prediction about the branch instruction or could not perform that branch prediction. When the compiler could not perform the branch prediction, the selector selects an output from a conditional branch prediction device (saturation counter section). When the compiler performed the branch prediction, the selector selects a prediction result by the compiler for a prediction in Agree mode. These selection results are used for setting a value of a register holding the next address. Based on this next-address register value, an instruction is fetched from the cache then inserted into a pipeline.

摘要翻译： 下一个地址计算部分包含选择器并连接到指令高速缓存。 指令高速缓存维护分支指令的预解码结果或此分支指令中字段的预定义设置。 基于保存在指令高速缓存中的信息，选择器确定编译器是否执行关于分支指令的分支预测或者不能执行该分支预测。 当编译器不能执行分支预测时，选择器从条件分支预测装置（饱和度计数器部分）中选择输出。 当编译器执行分支预测时，选择器在同意模式下选择编译器预测的预测结果。 这些选择结果用于设置保存下一个地址的寄存器的值。 基于该下一个地址寄存器值，从缓存中取出指令，然后插入到管道中。

公开(公告)号：US5996014A

公开(公告)日：1999-11-30

申请号：US959844

申请日：1997-10-29

申请人： Ikuo Uchihori ,  Shigehiro Asano ,  Masayuki Takakuwa ,  Tatsunori Kanai

发明人： Ikuo Uchihori ,  Shigehiro Asano ,  Masayuki Takakuwa ,  Tatsunori Kanai

IPC分类号： G06F3/06 ,  G06F13/00 ,  G06F15/16 ,  G11B19/02 ,  H04N21/218 ,  H04N21/2315

CPC分类号： H04N21/2182 ,  H04N21/222

摘要： The shared disk array which incorporates a plurality of disk apparatus storing the contents including the digitized video data and a plurality of element servers are connected to the shared channel network suitable for the multi-initiator architecture, whereby each of the element servers can physically share the shared disk array via the shared channel network. Further, each of the element servers is provided with the network interface suitable for the high-speed transmission and the band-width reservation, so that the contents stored in the shared disk array are read out in response to the request form the client, thus being output of the communication network via the network interface.

摘要翻译： 包含存储包括数字化视频数据的内容的多个磁盘装置的共享磁盘阵列和多个元件服务器连接到适合于多启动器架构的共享信道网络，由此每个元件服务器可以物理共享 共享磁盘阵列通过共享通道网络。 此外，每个元件服务器设置有适于高速传输和带宽预留的网络接口，使得响应于客户端的请求读出存储在共享磁盘阵列中的内容，因此 通过网络接口输出通信网络。

公开(公告)号：US5744535A

公开(公告)日：1998-04-28

申请号：US727105

申请日：1996-10-08

申请人： Tomohiko Akagawa ,  Ikunori Sakai ,  Shigehiro Asano

发明人： Tomohiko Akagawa ,  Ikunori Sakai ,  Shigehiro Asano

IPC分类号： C08L53/00 ,  C08K3/34

CPC分类号： C08L53/00

摘要： A polypropylene resin composition having a high moldability and capable of forming therefrom shaped articles having excellent surface hardness, thermal deformation resistance and low temperature impact resistance includes (A) 35-74 wt % of a crystalline ethylene-propylene block copolymer with an ethylene content of 0.5-15 wt %, an isotactic pentad fractional propylene of 96% or more and a MFR of 40-80 g/10 min. (230.degree. C., 2160 g); (B) 21-40 wt % of an ethylene-.alpha.-olefin copolymer produced by using a single site catalyst and having an .alpha.-olefin content of 70 mol % or more, a ratio (Mw/Mn) of 2.5 or less, and a ratio (MI.sub.10 /MI.sub.2.16) of 6 to 15; and (C) 5-25 wt % of a talc particle component having an average particle size of 3-7 .mu.m.

摘要翻译： 具有高成型性并且能够形成具有优异的表面硬度，耐热变形性和耐低温冲击性的成形制品的聚丙烯树脂组合物包括（A）35-74重量％的乙烯含量的结晶乙烯 - 丙烯嵌段共聚物 0.5-15重量％，全同立构五单元组分数丙烯为96％以上，MFR为40〜80g / 10分钟。 （230℃，2160g）; （B）21-40重量％的使用单中心催化剂制备的α-烯烃含量为70摩尔％以上，（Mw / Mn）为2.5以下的乙烯-α-烯烃共聚物，和 比例（MI10 / MI2.16）为6至15; 和（C）5-25重量％的平均粒径为3-7μm的滑石颗粒组分。