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公开(公告)号：US20050165987A1
公开(公告)日：2005-07-28
申请号：US10764626
申请日：2004-01-26
申请人： Shigehiro Asano , Peichun Liu , David Mui
发明人： Shigehiro Asano , Peichun Liu , David Mui
IPC分类号： G06F13/362 , G06F13/14 , G06F13/36
CPC分类号： G06F13/3625
摘要： Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.
摘要翻译： 用于控制一组代理对资源的访问的系统和方法，其中代理具有与其相关联的相应优先级，以及与资源控制相关联的监视器，以及由代理基于优先级访问资源的位置。 一个实施例在具有连接到处理器总线的多个处理器的计算机系统中实现。 处理器总线包括整形监视器，其被配置为控制处理器对总线的访问。 整形监视器根据分配给处理器的优先级，尝试在整个基期内分配来自每个处理器的访问。 整形监视器根据其相对优先级向处理器分配插槽。 首先根据处理器的各自的带宽需求分配优先级，但是可以基于对总线的实际访问和期望访问的比较来修改优先级。
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公开(公告)号：US20050111354A1
公开(公告)日：2005-05-26
申请号：US10718302
申请日：2003-11-20
申请人： Shigehiro Asano , Charles Johns , Matthew King , Peichun Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Johns , Matthew King , Peichun Liu , David Mui , Jieming Qi
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。
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公开(公告)号：US08611368B2
公开(公告)日：2013-12-17
申请号：US13162917
申请日：2011-06-17
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
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公开(公告)号：US08483227B2
公开(公告)日：2013-07-09
申请号：US10718302
申请日：2003-11-20
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
IPC分类号： H04L12/56
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。
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公开(公告)号：US07107376B2
公开(公告)日：2006-09-12
申请号：US10764626
申请日：2004-01-26
申请人： Shigehiro Asano , Peichun Peter Liu , David Mui
发明人： Shigehiro Asano , Peichun Peter Liu , David Mui
IPC分类号： G06F13/362 , G06F13/372
CPC分类号： G06F13/3625
摘要： Systems and methods for controlling access by a set of agents to a resource, where the agents have corresponding priorities associated with them, and where a monitor associated with the resource controls accesses by the agents to the resource based on the priorities. One embodiment is implemented in a computer system having multiple processors that are connected to a processor bus. The processor bus includes a shaping monitor configured to control access by the processors to the bus. The shaping monitor attempts to distribute the accesses from each of the processors throughout a base period according to priorities assigned to the processors. The shaping monitor allocates slots to the processors in accordance with their relative priorities. Priorities are initially assigned according to the respective bandwidth needs of the processors, but may be modified based upon comparisons of actual to expected accesses to the bus.
摘要翻译： 用于控制一组代理对资源的访问的系统和方法，其中代理具有与其相关联的相应优先级，以及与资源控制相关联的监视器，以及由代理基于优先级访问资源的位置。 一个实施例在具有连接到处理器总线的多个处理器的计算机系统中实现。 处理器总线包括整形监视器，其被配置为控制处理器对总线的访问。 整形监视器根据分配给处理器的优先级，尝试在整个基期内分配来自每个处理器的访问。 整形监视器根据其相对优先级向处理器分配插槽。 首先根据处理器的各自的带宽需求分配优先级，但是可以基于对总线的实际访问和期望访问的比较来修改优先级。
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公开(公告)号：US20110246695A1
公开(公告)日：2011-10-06
申请号：US13162917
申请日：2011-06-17
申请人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
发明人： Shigehiro Asano , Charles Ray Johns , Matthew Edward King , Peichun Peter Liu , David Mui , Jieming Qi
IPC分类号： G06F12/00
CPC分类号： H04L41/0896
摘要： Disclosed is an apparatus which operates to substantially evenly distribute commands and/or data packets issued from a managed program or other entity over a given time period. The even distribution of these commands or data packets minimizes congestion in critical resources such as memory, I/O devices and/or the bus for transferring the data between source and destination. Any unmanaged commands or data packets are treated as in conventional technology.
摘要翻译： 公开了一种操作以在给定时间段内基本上均匀分布从被管理程序或其他实体发出的命令和/或数据分组的装置。 这些命令或数据分组的均匀分布最大限度地减少了诸如存储器，I / O设备和/或用于在源和目的地之间传送数据的总线的关键资源的拥塞。 任何非托管命令或数据包都按常规技术处理。
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公开(公告)号：US08812774B2
公开(公告)日：2014-08-19
申请号：US13217461
申请日：2011-08-25
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F11/1068
摘要： According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.
摘要翻译： 根据一个实施例，存储器系统包括每个具有多个块的半导体存储器; 第一张桌子 接收单元; 发电机组; 第二个表 和书写单位。 第一表包括多个存储区，每个存储区与每个块相关联，并且每个存储区存储缺陷信息。 生成单元基于指示第一表和第一表中的多行的索引号，选择要在每个半导体存储器中写入数据的一个块来生成一组块。 在第二表中，对于每个逻辑块地址彼此相关联地存储索引号和通道号。 当接收单元接收到写入命令时，写入单元将数据写入与构成该组的块中的所选频道号相关联的块。
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公开(公告)号：US08612824B2
公开(公告)日：2013-12-17
申请号：US13038804
申请日：2011-03-02
CPC分类号： G11C16/3418 , G11C16/00 , G11C29/028
摘要： A semiconductor memory device includes: plural semiconductor memory chips to store information depending on an amount of accumulated charge; plural parameter storage units provided in correspondence with the semiconductor memory chips, each parameter to store therein a parameter that defines an electrical characteristic of a signal used for writing information into or reading information from a corresponding one of the semiconductor memory chips; an error correction encoding unit configured to generate a first correction code capable of correcting an error in the information stored in a number of semiconductor memory chips no greater than a predetermined number out of the semiconductor memory chips, from the information stored in the semiconductor memory chips; and a parameter processing unit configured to change the parameters respectively corresponding to the number of semiconductor memory chips no greater than the predetermined number, and write the parameters changed into the parameter storage units, respectively.
摘要翻译： 半导体存储器件包括：多个半导体存储器芯片，用于根据累积电荷的量存储信息; 多个参数存储单元，与半导体存储器芯片对应地设置，每个参数用于存储定义用于将信息写入或从相应的一个半导体存储器芯片读取信息的信号的电特性的参数; 错误校正编码单元，被配置为从存储在半导体存储器芯片中的信息生成能够校正存储在半导体存储器芯片中的不大于预定数量的多个半导体存储器芯片中的信息中的误差的第一校正代码 ; 以及参数处理单元，被配置为分别对应于不大于预定数量的半导体存储器芯片的数量来分别改变参数，并将分别写入参数存储单元的参数进行写入。
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公开(公告)号：US08397017B2
公开(公告)日：2013-03-12
申请号：US12723846
申请日：2010-03-15
IPC分类号： G06F13/00
CPC分类号： G06F12/0246 , G06F3/061 , G06F3/064 , G06F3/0679 , G06F2212/7207
摘要： A volatile management memory stores management information for managing a use state of a storage medium. A management information storing unit divides the management information into plural division pieces and individually stores them in the storage medium. A main controller receives a command from a host device while the division pieces are being stored, performs data processing for the storage medium in response to the command between each division piece is stored, updates the management information divided into the division pieces according to the data processing content, and creates a log representing an update content of the management information. A log storing unit stores the log in the storage medium. A restoring unit reads the division pieces stored in the storage medium to the management memory as the management information, updates the management information according to the log stored in the storage medium, and restores the updated management information.
摘要翻译： 易失性管理存储器存储用于管理存储介质的使用状态的管理信息。 管理信息存储单元将管理信息分成多个分割片，并将它们分别存储在存储介质中。 主控制器在存储分割片的同时从主机装置接收命令，根据存储各分割片之间的命令对存储介质执行数据处理，根据数据更新分割成分割片的管理信息 处理内容，并创建表示管理信息的更新内容的日志。 日志存储单元将日志存储在存储介质中。 恢复单元将存储在存储介质中的分割信息作为管理信息读取到管理存储器，根据存储在存储介质中的日志更新管理信息，并恢复更新的管理信息。
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10.发明授权Semiconductor device and data processing method performed by semiconductor device to perform a repeat operation within a reconfigurable pipeline 失效由半导体器件执行的半导体器件和数据处理方法，以在可重新配置的管线内执行重复操作公开(公告)号：US08359457B2
公开(公告)日：2013-01-22
申请号：US12372011
申请日：2009-02-17
申请人： Takashi Yoshikawa , Shigehiro Asano
发明人： Takashi Yoshikawa , Shigehiro Asano
CPC分类号： G06F9/3879 , G06F9/3897 , G06F15/7867 , Y02D10/12 , Y02D10/13
摘要： The semiconductor device includes a controller and a plurality of dynamically reconfigurable circuits connected to one another in series below the controller to perform operations in the manner of a pipeline. The controller inputs data and reconfiguration information to the first one of the dynamically reconfigurable circuits. Each of the dynamically reconfigurable circuits includes a processing unit that performs a data computation, an updating unit that updates the reconfiguration information, and a repetition controlling unit that determines whether to repeat the computation and controls the data and the reconfiguration information.
摘要翻译： 半导体器件包括控制器和多个在控制器下串联连接的可动态可重构电路，以以管道的方式执行操作。 控制器将数据和重配置信息输入到动态可重配置电路中的第一个。 每个动态可重配置电路包括执行数据计算的处理单元，更新重新配置信息的更新单元以及确定是否重复计算并控制数据和重新配置信息的重复控制单元。
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