利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

138 条记录 (耗时 0.029 秒)

    Providing error correction coding for probed data
    91.
    发明申请
    Providing error correction coding for probed data 有权
    为探测数据提供纠错编码

    公开(公告)号：US20080163034A1

    公开(公告)日：2008-07-03

    申请号：US11647039

    申请日：2006-12-28

    申请人： Larry Tate ,  Richard Glass ,  Sanjay Dabral ,  Colin Looi

    发明人： Larry Tate ,  Richard Glass ,  Sanjay Dabral ,  Colin Looi

    IPC分类号： G06F11/00

    CPC分类号： H04L1/0056 ,  H04L1/24

    摘要： In one embodiment, the present invention includes a method for receiving an error correction code for information from a first port of a first agent and receiving the information from a second port of the first agent by probing a first link under test that couples the first agent and a second agent. The code may be used to validate the information, e.g., in a probe receiver during test or debug operations. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括一种用于从第一代理的第一端口接收用于信息的纠错码并从第一代理的第二端口接收信息的方法，该方法是通过探测耦合第一代理 和第二代理。 该代码可用于验证信息，例如在测试或调试操作期间的探测接收器中。 描述和要求保护其他实施例。

    Cache based physical layer self test
    98.
    发明申请
    Cache based physical layer self test 有权
    基于缓存的物理层自检

    公开(公告)号：US20060005092A1

    公开(公告)日：2006-01-05

    申请号：US10882966

    申请日：2004-06-30

    申请人： Tim Frodsham ,  Lakshminarayan Krishnamurty ,  Naveen Cherukuri ,  Sanjay Dabral ,  David Dunning ,  Theodore Schoenborn

    发明人： Tim Frodsham ,  Lakshminarayan Krishnamurty ,  Naveen Cherukuri ,  Sanjay Dabral ,  David Dunning ,  Theodore Schoenborn

    IPC分类号： G01R31/28

    CPC分类号： G06F11/27

    摘要： A software self test engine is executed from a cache of a processor. The software self test engine is executed using an execution engine of the processor to perform a physical layer self test. The physical layer self test is performed by transmitting a test vector from the execution engine under control of the self test engine to an input/output (“I/O”) unit of the processor along a datapath coupling the execution engine to the I/O unit. The test vector is transmitted along a loop back path including the I/O unit and the datapath to test a hardware device along the loop back path.

    摘要翻译： 从处理器的缓存执行软件自检引擎。 使用处理器的执行引擎执行软件自检引擎，以执行物理层自检。 通过在自检引擎的控制下将来自执行引擎的测试向量发送到处理器的输入/输出（“I / O”）单元，沿着将执行引擎耦合到I / O的数据通路执行物理层自检， O单位。 测试向量沿着包括I / O单元和数据通路的环回路径传输，以沿着循环路径测试硬件设备。

    Method and apparatus for a linearized output driver and terminator
    100.
    发明授权
    Method and apparatus for a linearized output driver and terminator 有权
    线性化输出驱动器和终端器的方法和装置

    公开(公告)号：US06646324B1

    公开(公告)日：2003-11-11

    申请号：US09609434

    申请日：2000-06-30

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L2900

    CPC分类号： H01L29/66659 ,  H01L29/7835 ,  Y02P80/30

    摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

    摘要翻译： 描述了用于线性化输出驱动器和终止器的方法和装置。 在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。 该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。 该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。 该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器 基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。