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    Diode and transistor design for high speed I/O
    1.
    发明授权
    Diode and transistor design for high speed I/O 失效
    用于高速I / O的二极管和晶体管设计

    公开(公告)号：US6137143A

    公开(公告)日：2000-10-24

    申请号：US107351

    申请日：1998-06-30

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L27/02 ,  H01L23/62

    CPC分类号： H01L27/0255 ,  H01L2924/0002

    摘要： An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

    摘要翻译： 一种集成电路，其包括占用集成电路基板的第一区域的性能电路和耦合到所述性能电路并且占据与所述第一区域分离的集成电路基板的第二区域的保护电路。 此外，形成集成电路的方法包括以下步骤：形成占据集成电路基板的第一区域的性能电路，形成与第一区域分离的占据集成电路的第二区域的保护电路，以及耦合保护 电路到性能电路。

    Method of fabricating a linearized output driver and terminator
    2.
    发明授权
    Method of fabricating a linearized output driver and terminator 有权
    制造线性化输出驱动器和终端器的方法

    公开(公告)号：US07250333B2

    公开(公告)日：2007-07-31

    申请号：US10394977

    申请日：2003-03-20

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L21/8234 ,  H01L21/8244

    CPC分类号： H01L29/66659 ,  H01L29/7835 ,  Y02P80/30

    摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

    摘要翻译： 描述了用于线性化输出驱动器和终止器的方法和装置。 在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。 该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。 该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。 该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器 基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。

    Diode and transistor design for high speed I/O
    3.
    发明授权
    Diode and transistor design for high speed I/O 失效

    公开(公告)号：US07012304B1

    公开(公告)日：2006-03-14

    申请号：US09651385

    申请日：2000-08-29

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0255 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit including a performance circuit occupying a first area of an integrated circuit substrate and a protection circuit coupled to the performance circuit and occupying a second area of an integrated circuit substrate separate from the first area. Also, a method of forming an integrated circuit including the steps of: Forming a performance circuit occupying a first area of an integrated circuit substrate, forming a protection circuit occupying a second area of an integrated circuit separate from the first area, and coupling the protection circuit to the performance circuit.

    Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances
    5.
    发明授权
    Method to reduce timing skews in I/O circuits and clock drivers caused by fabrication process tolerances 失效
    减少由制造工艺公差引起的I / O电路和时钟驱动器中的时序偏差的方法

    公开(公告)号：US06480059B2

    公开(公告)日：2002-11-12

    申请号：US09473855

    申请日：1999-12-28

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L2500

    CPC分类号： H03L7/00 ,  G06F13/4072 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/823828 ,  H01L29/4238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of reducing random, processing-induced timing variations in a field effect transistor device includes providing a semiconductor substrate having an active area, and forming a transistor having a gate over a portion of the active area, the gate having a first leg and a second leg. In a further aspect, a method of improving the timing skew of critically-matched circuits is presented. In a still further aspect of the invention, a field effect transistor and an integrated circuit device that can be used to improve timing robustness in the presence of random fabrication- or process-induced variations are presented.

    摘要翻译： 降低场效应晶体管器件中的随机处理引起的时序变化的方法包括提供具有有源区的半导体衬底，以及形成在有源区的一部分上具有栅极的晶体管，栅极具有第一支脚和 第二条腿 在另一方面，提出了一种改进严格匹配电路的定时偏移的方法。 在本发明的另一方面，提出了一种场效应晶体管和集成电路器件，其可用于在存在随机制造或工艺引起的变化的情况下改善时序鲁棒性。

    Method and apparatus for a linearized output driver and terminator
    6.
    发明授权
    Method and apparatus for a linearized output driver and terminator 有权
    线性化输出驱动器和终端器的方法和装置

    公开(公告)号：US06646324B1

    公开(公告)日：2003-11-11

    申请号：US09609434

    申请日：2000-06-30

    申请人： Sanjay Dabral ,  Krishna Seshan

    发明人： Sanjay Dabral ,  Krishna Seshan

    IPC分类号： H01L2900

    CPC分类号： H01L29/66659 ,  H01L29/7835 ,  Y02P80/30

    摘要： A method and apparatus for a linearized output driver and terminator is described. In one embodiment the method includes forming a gate electrode on a substrate, the portion of the substrate covered by the gate electrode defining a channel. The method further includes forming a first source/drain doped region on laterally opposed sides of the gate electrode in the substrate. The method also includes forming a spacer on laterally opposed sides of the gate electrode on the substrate. The method also includes forming a linearized drain contact region at a location within the first source/drain doped region sufficiently distant from the gate electrode to define a series resistor in the first source/drain doped region disposed between the gate electrode and the linearized drain contact area based on an expected resistivity of the source/drain doped region, the series resistor coupled electrically to the channel.

    摘要翻译： 描述了用于线性化输出驱动器和终止器的方法和装置。 在一个实施例中，该方法包括在衬底上形成栅电极，衬底的由栅电极覆盖的部分限定沟道。 该方法还包括在衬底的栅电极的横向相对侧上形成第一源极/漏极掺杂区域。 该方法还包括在基板上的栅电极的横向相对侧上形成间隔物。 该方法还包括在与栅电极充分远的第一源极/漏极掺杂区域内的位置处形成线性化的漏极接触区域，以在布置在栅极电极和线性化漏极接触之间的第一源极/漏极掺杂区域中限定串联电阻器 基于源极/漏极掺杂区域的预期电阻率的区域，串联电阻器电连接到沟道。