公开(公告)号：US08516352B2

公开(公告)日：2013-08-20

申请号：US12506327

申请日：2009-07-21

申请人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

发明人： Eran Sharon ,  Idan Alrod ,  Simon Litsyn

IPC分类号： H03M13/03

CPC分类号： H03M13/6362 ,  G06F11/1068 ,  H03M13/1111 ,  H03M13/15

摘要： k input bits are encoded according to a code with which is associated a m×n=m+k parity check matrix H. The resulting codeword is punctured, with n′

摘要翻译： k个输入位根据与m×n = m + k个奇偶校验矩阵H相关联的代码进行编码。所得码字被打孔，n'

公开(公告)号：US08508989B2

公开(公告)日：2013-08-13

申请号：US13183341

申请日：2011-07-14

申请人： Idan Alrod ,  Eran Sharon

发明人： Idan Alrod ,  Eran Sharon

IPC分类号： G11C11/34

CPC分类号： G11C11/5642 ,  G11C16/3418 ,  G11C2211/5634

摘要： A method of storing and reading data, using a memory that includes a plurality of cells (e.g. flash cells), such that data are stored in the cells by setting respective values of a physical parameter of the cells (e.g. threshold voltage) to be indicative of the data, and such that data are read from the cells by measuring those values. One of the cells and its neighbors are read. The data stored in the cell are estimated, based on the measurements and on respective extents to which the neighbors disturb the reading. Preferably, the method also includes determining those respective extents to which the neighbors disturb the reading, for example based on the measurements themselves.

摘要翻译： 一种使用包括多个单元（例如闪存单元）的存储器来存储和读取数据的方法，使得通过将单元的物理参数（例如阈值电压）的相应值设置为指示来存储在单元中的数据 的数据，并且通过测量这些值从单元读取数据。 读取其中一个单元及其邻居。 存储在单元中的数据基于测量以及相邻的干扰读数的相应范围来估计。 优选地，该方法还包括例如基于测量本身来确定邻近者对其进行干扰的相应范围。

公开(公告)号：US20130159599A1

公开(公告)日：2013-06-20

申请号：US13330185

申请日：2011-12-19

申请人： Shahar Bar-Or ,  Eran Sharon ,  Idan Alrod

发明人： Shahar Bar-Or ,  Eran Sharon ,  Idan Alrod

IPC分类号： G06F12/00

CPC分类号： G06F9/4418

摘要： The present application is directed to systems and methods for managing data in a device for hibernation states. In one implementation, the device includes an interface and a processor. The interface is coupled with a first memory and a second memory. The processor is in communication with the first and second memories via the interface. The processor is configured to read first data from the first memory, generate image data of the data stored in the first memory based on the first data, and write to the second memory prior to the device entering an initial hibernation state the image data of the data stored in the first memory. The processor is further configured to, after the device awakes from the initial hibernation state, read the image data from the second memory, reconstruct the first data based on the image data, and write the first data to the first memory.

摘要翻译： 本申请涉及用于管理用于休眠状态的设备中的数据的系统和方法。 在一个实现中，该设备包括接口和处理器。 接口与第一存储器和第二存储器耦合。 处理器经由接口与第一和第二存储器通信。 处理器被配置为从第一存储器读取第一数据，基于第一数据生成存储在第一存储器中的数据的图像数据，并且在设备进入初始休眠状态之前，向第二存储器写入第二数据的图像数据 数据存储在第一个存储器中。 处理器还被配置为在设备从初始休眠状态唤醒之后，从第二存储器读取图像数据，基于图像数据重建第一数据，并将第一数据写入第一存储器。

公开(公告)号：US20130031431A1

公开(公告)日：2013-01-31

申请号：US13280217

申请日：2011-10-24

申请人： Eran Sharon ,  Idan Alrod

发明人： Eran Sharon ,  Idan Alrod

IPC分类号： G06F11/273

CPC分类号： G11C16/3459 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/3481 ,  G11C2211/5641

摘要： Techniques for a post-write read are presented. In an exemplary embodiment, host data is initially written into the non-volatile memory in binary form, such as a non-volatile binary cache. It is then subsequently written from the binary section into a multi-state non-volatile section of the memory. After being written in multi-state format, pages of data from a multi-state block can then be checked against there source pages in the binary section to verify the quality of the multi-state write. This process can be performed on the memory device itself, without transferring the pages out to the controller.

摘要翻译： 介绍了写入后读取技术。 在示例性实施例中，主数据最初以二进制形式写入非易失性存储器，例如非易失性二进制高速缓存。 随后将其从二进制部分写入存储器的多状态非易失性部分。 在以多状态格式写入后，可以在二进制部分的源页面中检查来自多状态块的数据页面，以验证多状态写入的质量。 该过程可以在存储器设备本身上执行，而不将页面传送到控制器。

公开(公告)号：US20130028021A1

公开(公告)日：2013-01-31

申请号：US13332780

申请日：2011-12-21

申请人： Eran Sharon ,  Yan Li ,  Dana Lee ,  Idan Alrod

发明人： Eran Sharon ,  Yan Li ,  Dana Lee ,  Idan Alrod

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C29/04 ,  G11C11/5642 ,  G11C16/3459 ,  G11C29/50004 ,  G11C2211/5641

摘要： Techniques for a post-write read are presented. In an exemplary embodiment, a combined simultaneous sensing of multiple word lines is used in order to identify a problem in one or more of these word lines. That is, sensing voltages are concurrently applied to the control gates of more than one memory cell whose resultant conductance is measured on the same bit line. The combined sensing result is use for measuring certain statistics of the cell voltage distribution (CVD) of multiple word lines and comparing it to the expected value. In case the measured statistics are different than expected, this may indicate that one or more of the sensed word lines may exhibit a failure and more thorough examination of the group of word lines can be performed.

摘要翻译： 介绍了写入后读取技术。 在示例性实施例中，使用多个字线的组合同时感测以便识别这些字线中的一个或多个中的问题。 也就是说，感测电压同时施加到多个存储单元的控制栅极，其结果电导在同一位线上被测量。 组合的感测结果用于测量多个字线的单元电压分布（CVD）的某些统计量并将其与预期值进行比较。 在测量的统计量与预期不同的情况下，这可以指示感测字线中的一个或多个可能表现出故障，并且可以执行对该组字线的更彻底的检查。

公开(公告)号：US20120278687A1

公开(公告)日：2012-11-01

申请号：US13390855

申请日：2011-03-03

申请人： Eran Sharon ,  Idan Alrod

发明人： Eran Sharon ,  Idan Alrod

IPC分类号： H03M13/03 ,  G06F11/10

CPC分类号： G06F11/1048

摘要： A method of storing a set of metadata bits associated with each of multiple data words includes combining the set of metadata bits with each of the multiple data words to generate multiple extended data words. The method includes encoding each of the multiple extended data words to generate multiple codewords and puncturing each of the multiple codewords to generate multiple punctured codewords, where in each of the punctured codewords the set of metadata bits is removed. The method includes storing the multiple punctured codewords, transforming the set of metadata bits to generate a set of transformed metadata bits, and storing the set of transformed metadata bits.

摘要翻译： 存储与多个数据字中的每一个相关联的一组元数据位的方法包括将该组元数据位与多个数据字中的每一个组合以生成多个扩展数据字。 该方法包括对多个扩展数据字中的每一个进行编码以产生多个码字并对多个码字中的每一个进行删截以产生多个穿孔码字，其中在每个穿孔码字中去除元数据比特集合。 该方法包括存储多个穿孔码字，变换元数据比特集合以生成一组经变换的元数据比特，以及存储经转换的元数据比特组。

公开(公告)号：US08291279B2

公开(公告)日：2012-10-16

申请号：US12124192

申请日：2008-05-21

申请人： Eran Sharon ,  Simon Litsyn ,  Idan Alrod

发明人： Eran Sharon ,  Simon Litsyn ,  Idan Alrod

IPC分类号： H03M13/00

CPC分类号： H03M13/114 ,  H03M13/6505

摘要： To decode a representation of a codeword that encodes K information bits as N>K codeword bits, messages are exchanged between N bit nodes and N−K check nodes of a graph in which E edges connect the bit nodes and the check nodes. While messages are exchanged, fewer than E of the messages are stored, and/or fewer than N soft estimates of the codeword bits are stored. In some embodiments, the messages are exchanged only within sub-graphs and between the sub-graphs and one or more external check nodes. While messages are exchanged, the largest number of stored messages is the number of edges in the sub-graph with the most edges plus the number of edges that connect the sub-graphs to the external check node(s), and/or the largest number of stored soft estimates is the number of bit nodes in the sub-graph with the most bit nodes.

摘要翻译： 为了将编码K个信息比特的码字的表示解码为N个K个码字比特，消息在其中E个边缘连接比特节点和校验节点的图的N个比特节点和N-K个校验节点之间进行交换。 当消息被交换时，存储少于E个消息，和/或存储少于N个码字比特的软估计。 在一些实施例中，消息仅在子图中以及子图和一个或多个外部校验节点之间交换。 当消息被交换时，最大数量的存储消息是具有最多边缘的子图中的边数加上将子图连接到外部校验节点的边数，和/或最大 存储的软估计数是具有最多位节点的子图中的比特节点的数量。

公开(公告)号：US08261176B2

公开(公告)日：2012-09-04

申请号：US12495654

申请日：2009-06-30

申请人： Idan Alrod ,  Eran Sharon

发明人： Idan Alrod ,  Eran Sharon

IPC分类号： G06F11/00 ,  G06F7/22 ,  H03M13/00

CPC分类号： H03M13/1555 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/158 ,  H03M13/159 ,  H03M13/6561

摘要： Systems and methods to perform polynomial division are disclosed. In a particular embodiment, the method includes receiving a codeword and storing a portion of the received codeword at a register. The portion of the received codeword has a first number of terms. A divisor having a second number of terms is also received. During at least one stage of a multi-stage polynomial division operation using the portion of the codeword and the divisor, the portion of the received codeword to be divided by the divisor is adjusted based on a result of a comparison of the first number to the second number.

摘要翻译： 公开了执行多项式除法的系统和方法。 在特定实施例中，该方法包括接收码字并将接收的码字的一部分存储在寄存器中。 所接收的码字的部分具有第一数目的项。 还收到了具有第二数目条款的除数。 在使用码字和除数的部分的多级多项式除法运算的至少一个阶段期间，基于第一数字与第二数字的比较的结果来调整要除以除数的接收码字的部分 第二个数字。

公开(公告)号：US08261157B2

公开(公告)日：2012-09-04

申请号：US12264959

申请日：2008-11-05

申请人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

发明人： Simon Litsyn ,  Idan Alrod ,  Eran Sharon ,  Mark Murin ,  Menahem Lasser

IPC分类号： H03M13/00

CPC分类号： G06F11/1072

摘要： A plurality of logical pages is stored in a MBC flash memory along with corresponding ECC bits, with at least one of the MBC cells storing bits from more than one logical page, and with at least one of the ECC bits applying to two or more of the logical pages. When the pages are read from the memory, the data bits as read are corrected using the ECC bits as read. Alternatively, a joint, systematic or non-systematic ECC codeword is computed for two or more of the logical pages and is stored instead of those logical pages. When the joint codeword is read, the logical bits are recovered from the codeword as read. The scope of the invention also includes corresponding memory devices, the controllers of such memory devices, and also computer-readable storage media bearing computer-readable code for implementing the methods.

摘要翻译： 多个逻辑页面与对应的ECC位一起存储在MBC闪速存储器中，其中至少一个MBC单元存储来自多于一个的逻辑页面的位，以及至少一个ECC位应用于两个或多个 逻辑页面。 当从存储器中读取页面时，读取的数据位使用读取的ECC位进行校正。 或者，针对两个或多个逻辑页面计算联合的，系统的或非系统的ECC码字，并且存储该代码字而不是那些逻辑页面。 当读取联合码字时，从读取的码字中恢复逻辑比特。 本发明的范围还包括对应的存储器件，这种存储器件的控制器，以及用于实现该方法的具有计算机可读代码的计算机可读存储介质。

公开(公告)号：US20120163085A1

公开(公告)日：2012-06-28

申请号：US12978368

申请日：2010-12-23

申请人： Idan Alrod ,  Eran Sharon ,  Toru Miwa ,  Gerrit Jan Hemink ,  Nima Mokhlesi

发明人： Idan Alrod ,  Eran Sharon ,  Toru Miwa ,  Gerrit Jan Hemink ,  Nima Mokhlesi

IPC分类号： G11C16/26

CPC分类号： G11C16/34 ,  G06F11/1072 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3422 ,  G11C16/3427 ,  G11C29/00

摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”.

摘要翻译： 非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。 当读取相对于第一组参考阈值时，获得硬比特。 相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。 软位是通过对当前字线WLn上的电压的第一次调制和相邻字线WLn + 1上的电压的第二调制的组合产生的，如在称为“直读先锋（DLA）”的读取方案中 。