公开(公告)号：US09362384B2

公开(公告)日：2016-06-07

申请号：US14559542

申请日：2014-12-03

申请人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

发明人： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC分类号： H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

公开(公告)号：US07518192B2

公开(公告)日：2009-04-14

申请号：US10985532

申请日：2004-11-10

申请人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

发明人： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

IPC分类号： H01L23/62

CPC分类号： H01L21/76816 ,  H01L27/0274 ,  H01L29/78

摘要： A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.

摘要翻译： 提出了一种用于静电放电保护的半导体结构。 半导体结构包括具有衬底，栅极电极，源极区域和漏极区域的接地栅极nMOS（GGNMOS）。 在源极和漏极侧形成多个接触插塞。 多个第一级通孔电耦合到GGNMOS并且在源极和漏极区域中具有基本不对称的布局。 第二级通过将ESD电流重新路由到期望的第一级通孔。 GGNMOS中电流的均匀性得到改善。

公开(公告)号：US07485930B2

公开(公告)日：2009-02-03

申请号：US11622574

申请日：2007-01-12

申请人： Jian-Hsing Lee ,  Shui-Hunyi Chen

发明人： Jian-Hsing Lee ,  Shui-Hunyi Chen

IPC分类号： H01L23/62

CPC分类号： H01L27/0255

摘要： The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

摘要翻译： 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护器件和Vcc至Bss保护器件的重掺杂P +保护环组成。 另外，在I / O保护器件的P +保护环周围还有一个重掺杂的N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

公开(公告)号：US20080211027A1

公开(公告)日：2008-09-04

申请号：US11713193

申请日：2007-03-01

申请人： Shu Huei Lin ,  Jian-Hsing Lee ,  Shao-Chang Huang ,  Cheng Hsu Wu ,  Chuan Ying Lee

发明人： Shu Huei Lin ,  Jian-Hsing Lee ,  Shao-Chang Huang ,  Cheng Hsu Wu ,  Chuan Ying Lee

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor.

摘要翻译： 一种连接到集成电路中的接合焊盘的静电放电（ESD）结构，包括：具有连接到低电压源（GND）的一个或多个第一P +区的P型衬底，形成在P型衬底中的第一Nwell 设置在所述第一Nwell内并连接到所述接合焊盘的一个或多个第二P +区域，设置在所述第一N阱之外但在所述P型衬底中并连接到所述GND的至少一个第一N +区域，设置至少一个第二N +区域 在第一N阱之外，但在P型衬底中并连接到焊盘，其中第二N +区域比第一N +区域远离第一Nwell区域，并且至少一个导电材料设置在P型衬底之上 第一N +区和第二N +区，并且耦合到GND，其中第一N +区，第二N +区和导电材料分别形成NMOS晶体管的源极，漏极和栅极，并且第一P +区域更远 从第一个Nwell比NMOS晶体管。

公开(公告)号：US20080137244A1

公开(公告)日：2008-06-12

申请号：US11637108

申请日：2006-12-12

申请人： Kuo-Feng Yo ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu-Chin Yang

发明人： Kuo-Feng Yo ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu-Chin Yang

IPC分类号： H02H9/00

CPC分类号： H01L27/0262

摘要： An electrostatic discharge (ESD) protection circuit. The ESD protection circuit comprises a silicon controlled rectifier (SCR) device and a metal-oxide-semiconductor (MOS) triggering device. The SCR device has a cathode connected to a first fixed potential and an anode. The MOS triggering device has a gate and a source connected to the first fixed potential and a drain connected to the anode. In addition, the MOS triggering device is not physically disposed in the SCR device.

摘要翻译： 静电放电（ESD）保护电路。 ESD保护电路包括可控硅整流器（SCR）器件和金属氧化物半导体（MOS）触发器件。 SCR器件具有连接到第一固定电位和阳极的阴极。 MOS触发装置具有连接到第一固定电位的栅极和源极以及连接到阳极的漏极。 此外，MOS触发装置没有物理地设置在SCR装置中。

公开(公告)号：US07372083B2

公开(公告)日：2008-05-13

申请号：US11199662

申请日：2005-08-09

申请人： Jian-Hsing Lee ,  Yu-Chang Jong

发明人： Jian-Hsing Lee ,  Yu-Chang Jong

IPC分类号： H01L29/72

CPC分类号： H01L29/7393 ,  H01L27/0262 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/7436

摘要： A high voltage p-type metal oxide semiconductor (HVPMOS) device having electrostatic discharge (ESD) protection functions and a method of forming the same are provided. The HVPMOS includes a PMOS transistor, wherein the PMOS transistor comprises a first source/drain region doped with a p-type impurity in a high voltage p-well (HVPW) region, a second source/drain region doped with a p-type impurity in a high voltage n-well (HVNW) region wherein the HVPW region and HVNW region physically contact each other, a field region substantially underlying a gate dielectric, and a first heavily doped n-type (N+) region in the HVPW region and contacting the first source/drain region. The device further includes an N+ buried layer underlying the HVPW region and the HVNW region and a p-type substrate underlying the N+ buried layer. The device has robust performance for both forward and reverse mode ESD.

摘要翻译： 提供了具有静电放电（ESD）保护功能的高电压p型金属氧化物半导体（HVPMOS）器件及其形成方法。 HVPMOS包括PMOS晶体管，其中PMOS晶体管包括在高压p阱（HVPW）区域中掺杂有p型杂质的第一源极/漏极区域，掺杂有p型杂质的第二源极/漏极区域 在HVPW区域和HVNW区域彼此物理接触的场合，HVPW区域中基本上位于栅极电介质的场区域和第一重掺杂n型（N +）区域的高电压n阱（HVNW）区域中， 第一源极/漏极区域。 该器件还包括位于HVPW区域和HVNW区域下面的N +掩埋层和位于N +掩埋层下面的p型衬底。 该器件具有强大的正向和反向模式ESD性能。

公开(公告)号：US07179691B1

公开(公告)日：2007-02-20

申请号：US10207545

申请日：2002-07-29

申请人： Jian-Hsing Lee ,  Shui Hun Yi Chen

发明人： Jian-Hsing Lee ,  Shui Hun Yi Chen

IPC分类号： H01L21/332 ,  H01L21/331

CPC分类号： H01L27/0255

摘要： The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Vss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device and its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

摘要翻译： 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护装置和Vcc至Vss保护装置的重掺杂P +保护环组成。 此外，还有一个围绕I / O保护器件及其P +保护环的重掺杂N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

公开(公告)号：US20060157791A1

公开(公告)日：2006-07-20

申请号：US11037868

申请日：2005-01-18

申请人： Jian-Hsing Lee ,  Fu-Liang Yang ,  Chien-Chao Huang

发明人： Jian-Hsing Lee ,  Fu-Liang Yang ,  Chien-Chao Huang

IPC分类号： H01L23/62

CPC分类号： H01L27/1203 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection device. A first-type well is formed on an insulating layer. First and second second-type doped regions are formed on the first-type well. A first body-tie region is formed on the first-type well and is connected to one side of the first and the second second-type doped regions. A polysilicon gate layer is formed on the first-type well and the body-tie region, and is located between the first and the second second-type doped regions. The first first-type doped region is connected to the first body-tie region. The second first-type doped region is formed on the first-type well.

摘要翻译： ESD保护装置。 在绝缘层上形成第一型阱。 第一和第二二次掺杂区形成在第一型阱上。 在第一类型阱上形成第一结扎区，并连接到第一和第二第二类型掺杂区的一侧。 多晶硅栅层形成在第一型阱和体结区上，位于第一和第二第二掺杂区之间。 第一第一掺杂区域连接到第一贴合区域。 在第一型阱上形成第二第一掺杂区。

公开(公告)号：US06879203B2

公开(公告)日：2005-04-12

申请号：US10821270

申请日：2004-04-08

申请人： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

发明人： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC分类号： H01L23/62 ,  H01L27/02 ,  H01L29/74 ,  H01L29/768 ,  H03K5/08

CPC分类号： H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides two circuit embodiments for a whole chip electrostatic discharge, ECD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

摘要翻译： 本发明提供了用于整个芯片静电放电，ECD，保护方案的两个电路实施例。 它还包括一个全芯片ESD保护方法。 本发明涉及将本发明的电路分配给每个输入/输出焊盘，以便提供并联的ESD电流放电路径。 本发明的优点是能够快速地形成对地的平行放电路径，以便有效地放电损坏的ESD电流，以避免电路损坏。 两个电路实施例示出了本发明的保护电路如何在未分离的I / O焊盘和已加热的I / O焊盘两端均以并联电路连接，以快速放电ESD电流。 这些保护实施例需要少量的半导体区域，因为较小的保护电路分布并放置在每个I / O焊盘的位置。

公开(公告)号：US06803259B2

公开(公告)日：2004-10-12

申请号：US10404620

申请日：2003-03-31

申请人： Jian-Hsing Lee

发明人： Jian-Hsing Lee

IPC分类号： H01L21332

CPC分类号： H01L27/0262 ,  H01L29/74

摘要： A silicon controlled rectifier for SiGe process. The silicon controlled rectifier comprises a substrate, a buried layer of a first conductivity type in the substrate, a well of the first conductivity type in the substrate and above the buried layer, a doped region of a second conductivity type in the well, a first conducting layer of the second conductivity type on the substrate, and a second conducting layer of the first conductivity type on the first conducting layer.