公开(公告)号：US20060066374A1

公开(公告)日：2006-03-30

申请号：US11043333

申请日：2005-01-27

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： H03L7/06

CPC分类号： H03K5/133 ,  G06F1/12 ,  H03K2005/00058 ,  H03K2005/00071 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A phase adjustment unit adjusts the phases of a plurality of external clocks successively shifted in phase, thereby generating a plurality of internal clocks having an equal phase difference between every adjacent transition edges thereof. The internal clocks are synthesized to generate a composite clock having equal pulse intervals. Thus, even when the semiconductor integrated circuit is supplied with external clocks of lower frequencies, it is possible to operate the semiconductor integrated circuit at high speed. For example, the internal circuit can be operated and tested at high speed by using a low-cost LSI tester having a low clock frequency. This can reduce the testing cost of the semiconductor integrated circuit, allowing a reduction in chip cost.

摘要翻译： 相位调整单元调整相位相移的多个外部时钟的相位，从而生成在其每个相邻过渡边缘之间具有相等相位差的多个内部时钟。 内部时钟被合成以产生具有相等脉冲间隔的复合时钟。 因此，即使在半导体集成电路被提供有较低频率的外部时钟的情况下，也可以高速地操作半导体集成电路。 例如，通过使用具有低时钟频率的低成本LSI测试仪，可以高速地操作和测试内部电路。 这可以降低半导体集成电路的测试成本，从而降低芯片成本。

公开(公告)号：US20060044879A1

公开(公告)日：2006-03-02

申请号：US11012148

申请日：2004-12-16

申请人： Shusaku Yamaguchi ,  Hiroyoshi Tomita

发明人： Shusaku Yamaguchi ,  Hiroyoshi Tomita

IPC分类号： G11C7/10

CPC分类号： G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076

摘要： A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask signal is inputted thereafter is provided.

摘要翻译： 一种半导体存储器件，包括从外部输入写入数据以缓冲写入数据的输入缓冲器以及在读取操作期间将输入缓冲器置于非活动状态的控制电路，并且当读取掩模 之后输入信号。

公开(公告)号：US06759884B2

公开(公告)日：2004-07-06

申请号：US10078340

申请日：2002-02-21

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： H03H1126

CPC分类号： G11C8/18

摘要： A variable delay circuit includes a first delay circuit having a plurality of first delay stages connected in cascade. The first delay circuit receives an input signal at the initial stage of the first delay stages. A second delay circuit has a plurality of second delay stages identical to the first delay stages. The second delay circuit is connected in cascade and receives a first timing signal at the initial stage of the second delay stages. A detecting circuit receives a second timing signal asynchronous to the first timing signal, and detects, of delayed timing signals outputted from each of the second delay stages, a delayed timing signal having a transition edge near a transition edge of the second timing signal. A selecting circuit selects a delayed signal outputted from the first delay stage corresponding to the second delay stage outputting the delayed timing signal detected by the detecting circuit.

摘要翻译： 可变延迟电路包括具有串联连接的多个第一延迟级的第一延迟电路。 第一延迟电路在第一延迟级的初始阶段接收输入信号。 第二延迟电路具有与第一延迟级相同的多个第二延迟级。 第二延迟电路级联连接并在第二延迟级的初始阶段接收第一定时信号。 检测电路接收与第一定时信号异步的第二定时信号，并且检测从每个第二延迟级输出的延迟定时信号具有靠近第二定时信号的转移边缘的过渡沿的延迟定时信号。 选择电路选择从与第二延迟级相对应的第一延迟级输出的延迟信号，输出由检测电路检测到的延迟定时信号。

公开(公告)号：US06661728B2

公开(公告)日：2003-12-09

申请号：US10061304

申请日：2002-02-04

申请人： Hiroyoshi Tomita ,  Shinnosuke Kamata

发明人： Hiroyoshi Tomita ,  Shinnosuke Kamata

IPC分类号： G11C700

CPC分类号： G11C5/147

摘要： A semiconductor memory device with a supply voltage generating circuit which can fine-tune its output voltages according to the frequency of a given clock signal. A reference voltage generator produces a plurality of different reference voltages. A clock signal receiver accepts a clock signal and supplies it to a period measurement unit for measurement of the cycle period of the given clock signal. A selector selects one of the produced reference voltages according to the clock period measured by the period measurement unit. A supply voltage generator produces a supply voltage corresponding to the selected reference voltage.

公开(公告)号：US06404221B1

公开(公告)日：2002-06-11

申请号：US09526746

申请日：2000-03-16

申请人： Tomohiro Kawakubo ,  Hiroyoshi Tomita

发明人： Tomohiro Kawakubo ,  Hiroyoshi Tomita

IPC分类号： G01R3126

CPC分类号： G01R19/16552

摘要： A voltage detecting circuit includes a constant-voltage source, a load part including a first transistor coupled to the constant-voltage source, and a detecting part which is connected to the load part and includes a second transistor of the same type as that of the first transistor. The detecting part detects a given voltage applied thereto.

摘要翻译： 电压检测电路包括恒压源，负载部分，包括耦合到恒压源的第一晶体管，以及检测部分，其连接到负载部分，并且包括与第二晶体管相同类型的第二晶体管 第一晶体管。 检测部分检测施加到其上的给定电压。

公开(公告)号：US06324113B1

公开(公告)日：2001-11-27

申请号：US09577498

申请日：2000-05-24

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： A semiconductor integrated circuit comprising: a pair of memory cores in which identical data are written; a refresh signal generating circuit; a refresh controlling circuit; and a read controlling circuit. The memory cores are operated during each predetermined period as refresh cores for performing a refresh operation and as read cores for performing a read operation. The refresh core performs refresh and write operations. The read core performs read and write operations. The write cycle time defined as an operation specification is set longer than the time necessary for each of the memory cores to perform a write operation. Therefore, during the refresh core, the time difference between the write cycle and the write operation is summed up during a plurality of write cycles to create a predetermined time margin. This time margin is utilized to perform a refresh operation so that the performance of the refresh operation, in conflict with the write operation, does not show to the exterior of the semiconductor integrated circuit. That is, even if a write operation is performed throughout the refresh core period, it is possible to prevent the data in the memory cores from being damaged. This enables users to use the semiconductor integrated circuit without taking refresh operations into consideration.

摘要翻译： 一种半导体集成电路，包括：一对存储器核，其中写入相同的数据; 刷新信号发生电路; 刷新控制电路; 和读控制电路。 在每个预定时段期间，存储器核心作为用于执行刷新操作的刷新核心以及用于执行读取操作的读取核心。 刷新内核执行刷新和写入操作。 读核心执行读写操作。 定义为操作规范的写周期时间被设置为比每个存储器核执行写操作所需的时间长。 因此，在刷新核心期间，在多个写周期期间将写入周期和写入操作之间的时间差相加以创建预定的时间裕度。 该时间裕度用于执行刷新操作，使得与写入操作冲突的刷新操作的性能不显示到半导体集成电路的外部。 也就是说，即使在刷新核心周期执行写入操作，也可以防止存储器核心中的数据被损坏。 这使得用户能够使用半导体集成电路而不考虑刷新操作。

公开(公告)号：US06304117B1

公开(公告)日：2001-10-16

申请号：US09635666

申请日：2000-08-10

申请人： Masafumi Yamazaki ,  Hiroyoshi Tomita

发明人： Masafumi Yamazaki ,  Hiroyoshi Tomita

IPC分类号： H03L706

CPC分类号： H03K5/133 ,  H03K5/131 ,  H03K2005/00058 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0818 ,  H03L7/087

摘要： A variable delay circuit includes a load on a signal transfer line, at least one transistor connected in parallel with the signal transfer line. Each transistor is controlled by a gate voltage thereof so that a signal on the signal transfer line is delayed in response to a magnitude of the gate capacitance connected thereto.

摘要翻译： 可变延迟电路包括信号传输线上的负载，与信号传输线并联连接的至少一个晶体管。 每个晶体管由其栅极电压控制，使得信号传输线上的信号响应于与其连接的栅极电容的大小而被延迟。

公开(公告)号：US06292428B1

公开(公告)日：2001-09-18

申请号：US09240007

申请日：1999-01-29

申请人： Hiroyoshi Tomita ,  Tatsuya Kanda

发明人： Hiroyoshi Tomita ,  Tatsuya Kanda

IPC分类号： G11C800

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C8/00 ,  G11C8/04 ,  G11C8/18

摘要： A semiconductor device which receives addresses in synchronism with a clock signal and receives data in synchronism with a strobe signal includes address-latch circuits, a first control circuit which selects one of the address-latch circuits in sequence in response to the clock signal, and controls the selected one of the address-latch circuits to latch a corresponding one of the addresses in response to the clock signal, and a second control circuit which selects one of the address-latch circuits in sequence in response to the strobe signal, and controls the selected one of the address-latch circuits to output a corresponding one of the addresses in response to the strobe signal.

摘要翻译： 与时钟信号同步地接收地址并与选通信号同步地接收数据的半导体器件包括地址锁存电路，响应于时钟信号依次选择地址锁存电路之一的第一控制电路，以及 控制所选择的一个地址锁存电路以响应于时钟信号锁存对应的一个地址;以及第二控制电路，其响应于选通信号依次选择一个地址锁存电路，并且控制 所选择的一个地址锁存电路响应于选通信号输出对应的一个地址。

公开(公告)号：US06275086B1

公开(公告)日：2001-08-14

申请号：US09385007

申请日：1999-08-27

申请人： Hiroko Douchi ,  Hiroyoshi Tomita

发明人： Hiroko Douchi ,  Hiroyoshi Tomita

IPC分类号： H03K513

CPC分类号： G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  H03K5/2481

摘要： A clock signal generator which is particularly useful for a double data rate SDRAM (DDR-SDRAM) includes two or more clock signal input buffers and an enable signal input buffer. The clock signal generator generates internal clock signals that fluctuate at substantially different timings, yet the relationship between the internal clock signals with respect to validation and invalidation timing is constant. A latch circuit latches an enable signal from the enable signal buffer in accordance with a first internal clock signal from a first one of the clock signal buffers. A first enable signal connected to the latch circuit holds the latched enable signal in accordance with the first internal clock signal. A second enable circuit receives the first enable signal and the first internal clock signal and generates a second enable signal used to activate the clock signal buffers. A logic gate receives the first enable signal and the first internal clock signal and controls the output of the first internal clock signal.

摘要翻译： 对双倍数据速率SDRAM（DDR-SDRAM）特别有用的时钟信号发生器包括两个或更多个时钟信号输入缓冲器和使能信号输入缓冲器。 时钟信号发生器产生以基本上不同的定时波动的内部时钟信号，但是内部时钟信号相对于验证和无效定时的关系是恒定的。 锁存电路根据来自第一个时钟信号缓冲器的第一内部时钟信号来锁存来自使能信号缓冲器的使能信号。 连接到锁存电路的第一使能信号根据第一内部时钟信号保持锁存使能信号。 第二使能电路接收第一使能信号和第一内部时钟信号，并产生用于激活时钟信号缓冲器的第二使能信号。 逻辑门接收第一使能信号和第一内部时钟信号并控制第一内部时钟信号的输出。

公开(公告)号：US06266294B1

公开(公告)日：2001-07-24

申请号：US09304516

申请日：1999-05-04

申请人： Masahiro Yada ,  Hiroyoshi Tomita

发明人： Masahiro Yada ,  Hiroyoshi Tomita

IPC分类号： G11C800

CPC分类号： G11C7/222 ,  G11C7/22

摘要： According to the present invention, in an integrated circuit device for receiving an external clock signal and a clock enable signal and for supplying to an internal circuit an internal clock signal which has a predetermined phase relationship with the external clock signal, a DLL circuit for generating a delay clock signal, synchronized and in phase with the external clock signal, is operated continuously even in a low power consumption mode, and the provision of the delay clock signal to the internal circuit is halted. When the mode is switched from the low power consumption mode to the normal mode, the delay clock signal generated by the DLL circuit, which is operated continuously, is supplied as an internal clock signal to the internal circuit again.

摘要翻译： 根据本发明，在用于接收外部时钟信号和时钟使能信号并用于向内部电路提供与外部时钟信号具有预定相位关系的内部时钟信号的集成电路装置中，用于产生 与外部时钟信号同步且同相的延迟时钟信号即使在低功耗模式下也连续工作，并且停止向内部电路提供延迟时钟信号。 当模式从低功耗模式切换到正常模式时，由连续操作的DLL电路产生的延迟时钟信号作为内部时钟信号被再次提供给内部电路。