公开(公告)号：US07719915B2

公开(公告)日：2010-05-18

申请号：US11653338

申请日：2007-01-16

申请人： Hiroyoshi Tomita ,  Shusaku Yamaguchi

发明人： Hiroyoshi Tomita ,  Shusaku Yamaguchi

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1045 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/4076

摘要： A multipurpose terminal receives an address signal and a data signal. An address valid terminal receives an address valid signal indicating that a signal supplied to the multipurpose terminal is the address signal. An arbiter determines which of an external access request and an internal refresh request is given priority. The arbiter disables reception of the internal fresh request in response to a fact that both a chip enable signal and the address valid signal reach a valid level (an external access request). The arbiter enables the reception of the internal refresh request in response to completion of read or write operation. As a result, in a semiconductor memory device including the multipurpose terminal which receives the address signal and the data signal, contention between the read operation and the write operation, and a refresh operation which responds to the internal refresh request is prevented, which prevents a malfunction.

摘要翻译： 多功能终端接收地址信号和数据信号。 地址有效终端接收地址有效信号，指示提供给多功能终端的信号是地址信号。 仲裁者确定哪个外部访问请求和内部刷新请求被赋予优先级。 响应于芯片使能信号和地址有效信号都达到有效电平（外部访问请求）的事实，仲裁器禁止接收内部新的请求。 响应于读或写操作的完成，仲裁器使得能够接收内部刷新请求。 结果，在包括接收地址信号和数据信号的多用途终端的半导体存储器件中，防止读取操作和写入操作之间的争用以及响应于内部刷新请求的刷新操作，这防止了 故障。

公开(公告)号：US20070109897A1

公开(公告)日：2007-05-17

申请号：US11653338

申请日：2007-01-16

申请人： Hiroyoshi Tomita ,  Shusaku Yamaguchi

发明人： Hiroyoshi Tomita ,  Shusaku Yamaguchi

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C7/1045 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/4076

摘要： A multipurpose terminal receives an address signal and a data signal. An address valid terminal receives an address valid signal indicating that a signal supplied to the multipurpose terminal is the address signal. An arbiter determines which of an external access request and an internal refresh request is given priority. The arbiter disables reception of the internal fresh request in response to a fact that both a chip enable signal and the address valid signal reach a valid level (an external access request). The arbiter enables the reception of the internal refresh request in response to completion of read or write operation. As a result, in a semiconductor memory device including the multipurpose terminal which receives the address signal and the data signal, contention between the read operation and the write operation, and a refresh operation which responds to the internal refresh request is prevented, which prevents a malfunction.

摘要翻译： 多功能终端接收地址信号和数据信号。 地址有效终端接收地址有效信号，指示提供给多功能终端的信号是地址信号。 仲裁者确定哪个外部访问请求和内部刷新请求被赋予优先级。 响应于芯片使能信号和地址有效信号都达到有效电平（外部访问请求）的事实，仲裁器禁止接收内部新的请求。 响应于读或写操作的完成，仲裁器使得能够接收内部刷新请求。 结果，在包括接收地址信号和数据信号的多用途终端的半导体存储器件中，防止读取操作和写入操作之间的争用以及响应于内部刷新请求的刷新操作，这防止了 故障。

公开(公告)号：US20080181023A1

公开(公告)日：2008-07-31

申请号：US12054961

申请日：2008-03-25

申请人： Shusaku YAMAGUCHI ,  Hiroyoshi Tomita

发明人： Shusaku YAMAGUCHI ,  Hiroyoshi Tomita

IPC分类号： G11C7/10

CPC分类号： G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076

摘要： A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask signal is inputted thereafter is provided.

摘要翻译： 一种半导体存储器件，包括从外部输入写入数据以缓冲写入数据的输入缓冲器以及在读取操作期间将输入缓冲器置于非活动状态的控制电路，并且当读取掩模 之后输入信号。

公开(公告)号：US07359253B2

公开(公告)日：2008-04-15

申请号：US11012148

申请日：2004-12-16

申请人： Shusaku Yamaguchi ,  Hiroyoshi Tomita

发明人： Shusaku Yamaguchi ,  Hiroyoshi Tomita

IPC分类号： G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076

摘要： A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask signal is inputted thereafter is provided.

摘要翻译： 一种半导体存储器件，包括从外部输入写入数据以缓冲写入数据的输入缓冲器以及在读取操作期间将输入缓冲器置于非活动状态的控制电路，并且当读取掩模 之后输入信号。

公开(公告)号：US07548465B2

公开(公告)日：2009-06-16

申请号：US12054961

申请日：2008-03-25

申请人： Shusaku Yamaguchi ,  Hiroyoshi Tomita

发明人： Shusaku Yamaguchi ,  Hiroyoshi Tomita

IPC分类号： G11C7/00

CPC分类号： G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076

摘要： A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask signal is inputted thereafter is provided.

摘要翻译： 一种半导体存储器件，包括从外部输入写入数据以缓冲写入数据的输入缓冲器以及在读取操作期间将输入缓冲器置于非活动状态的控制电路，并且当读取掩模 之后输入信号。

公开(公告)号：US20060044879A1

公开(公告)日：2006-03-02

申请号：US11012148

申请日：2004-12-16

申请人： Shusaku Yamaguchi ,  Hiroyoshi Tomita

发明人： Shusaku Yamaguchi ,  Hiroyoshi Tomita

IPC分类号： G11C7/10

CPC分类号： G11C7/1006 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/4076

摘要： A semiconductor memory device that includes an input buffer being inputted a write data from outside to buffer the write data and a control circuit putting the input buffer into an inactive state during a read operation and putting the input buffer into an active state when a read mask signal is inputted thereafter is provided.

摘要翻译： 一种半导体存储器件，包括从外部输入写入数据以缓冲写入数据的输入缓冲器以及在读取操作期间将输入缓冲器置于非活动状态的控制电路，并且当读取掩模 之后输入信号。

公开(公告)号：US20120225531A1

公开(公告)日：2012-09-06

申请号：US13473242

申请日：2012-05-16

申请人： Hiroyuki Ogawa ,  Hiroyoshi Tomita ,  Masato Takita

发明人： Hiroyuki Ogawa ,  Hiroyoshi Tomita ,  Masato Takita

IPC分类号： H01L21/02

CPC分类号： H01L27/0207 ,  G11C5/063 ,  G11C7/02 ,  G11C7/18 ,  G11C11/4097 ,  H01L27/1085 ,  H01L27/10885 ,  H01L27/10897

摘要： A semiconductor device includes a semiconductor substrate; a memory cell array including a plurality of memory cells formed on the semiconductor substrate and arranged in a matrix in a first direction and a second direction on the surface of the semiconductor substrate; a plurality of sense amplifiers formed on the semiconductor substrate and including a first sense amplifier and a second sense amplifier; and a plurality of bit lines extending along the first direction above the memory cell array, and arranged side by side in the second direction, wherein the plurality of bit lines include a first bit line pair formed in a first wiring layer and a second bit line pair formed in a second wiring layer located above the first wiring layer.

摘要翻译： 半导体器件包括半导体衬底; 存储单元阵列，包括形成在所述半导体衬底上并在所述半导体衬底的表面上沿第一方向和第二方向布置成矩阵的多个存储单元; 多个读出放大器，形成在半导体衬底上并包括第一读出放大器和第二读出放大器; 以及沿着存储单元阵列上方的第一方向延伸并沿第二方向并排布置的多个位线，其中多个位线包括形成在第一布线层中的第一位线对和第二位线 形成在位于第一布线层上方的第二布线层中。

公开(公告)号：US07723796B2

公开(公告)日：2010-05-25

申请号：US11902568

申请日：2007-09-24

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： H01L23/62

CPC分类号： G05F3/262 ,  H01L29/4238

摘要： A semiconductor device includes a current-mirror circuit including a first ring-shape gate, a second ring-shape gate, a first diffusion layer formed around the first ring-shape gate and the second ring-shape gate, a second diffusion layer formed inside the first ring-shape gate, a third diffusion layer formed inside the second ring-shape gate, an interconnect line electrically connecting the first ring-shape gate and the second ring-shape gate to a same potential, and an STI area formed around the first diffusion layer, wherein a first transistor corresponding to the first ring-shape gate and a second transistor corresponding to the second ring-shape gate constitute the current-mirror circuit, wherein gates of dummy transistors that do not function as transistors are situated between the STI area and the first and second ring-shape gates, and are arranged both in a first direction and in a second direction substantially perpendicular to the first direction.

摘要翻译： 一种半导体器件包括：电流镜电路，包括第一环形栅极，第二环形栅极，形成在第一环状栅极和第二环形栅极周围的第一扩散层，第二扩散层， 第一环形栅极，形成在第二环形栅极内部的第三扩散层，将第一环形栅极和第二环形栅极电连接到相同电位的互连线，以及形成在第二环形栅极周围的STI区域 第一扩散层，其中对应于第一环形栅极的第一晶体管和对应于第二环形栅极的第二晶体管构成电流镜电路，其中不用作晶体管的虚拟晶体管的栅极位于 STI区域和第​​一和第二环形门，并且布置在基本上垂直于第一方向的第一方向和第二方向上。

公开(公告)号：US07539042B2

公开(公告)日：2009-05-26

申请号：US11783318

申请日：2007-04-09

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： G11C11/24 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4074 ,  G11C11/401 ,  G11C29/50 ,  G11C2029/0403 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10829

摘要： The present invention suppresses the refresh failure of a DRAM due to the dispersion of a threshold of a MOSFET. The DRAM has a first unit for recording a set value of a back bias potential to be applied to a back gate of a cell transistor and a second unit for generating a back bias potential based on the set value of the back bias potential recorded in the first unit and supplying the generated back bias potential to the back gate, wherein when a threshold of a MOSFET which has a structure identical to the cell transistor and which has been fabricated in the same process as the cell transistor is greater than a target value which the cell transistor should have, a value shallower than the back bias potential for the target value is recorded in the second unit.

摘要翻译： 本发明抑制由于MOSFET的阈值的偏差引起的DRAM的刷新故障。 DRAM具有第一单元，用于记录要施加到单元晶体管的背栅的背偏置电位的设定值，以及用于产生背偏电位的第二单元，其基于记录在所述单元晶体管中的背偏电位的设定值 第一单元并将所产生的反向偏置电位提供给所述后栅极，其中当具有与所述单元晶体管相同的并且已经以与所述单元晶体管相同的工艺制造的结构的MOSFET的阈值大于目标值时， 单元晶体管应当具有比目标值的背偏电位浅的值被记录在第二单元中。

公开(公告)号：US07109775B2

公开(公告)日：2006-09-19

申请号：US11110685

申请日：2005-04-21

申请人： Hiroyoshi Tomita

发明人： Hiroyoshi Tomita

IPC分类号： H03H11/26

CPC分类号： H03H11/265 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/023 ,  G11C29/028 ,  H03K5/133 ,  H03K2005/00071

摘要： A delay circuit includes: an input signal line (IN) through which an input signal is inputted; a capacitor (106) charged with and discharging electric charge; a first switch (101) connected to the input signal line and operating according to the input signal when the capacitor is to be charged with electric charge; a second switch (102) connected to the input signal line and operating according to the input signal when the electric charge is to be discharged from the capacitor; and a comparison circuit (107) comparing a voltage of the capacitor and a reference voltage to output a delay signal of the input signal.

摘要翻译： 延迟电路包括：输入信号线（IN），输入信号经输入信号线输入; 充电并放电的电容器（106） 第一开关（101），连接到所述输入信号线，并且当所述电容器要被充电时根据所述输入信号进行操作; 第二开关（102），连接到输入信号线，并且当电荷从电容器放电时，根据输入信号进行操作; 以及将电容器的电压和参考电压进行比较以输出输入信号的延迟信号的比较电路（107）。