公开(公告)号：US08255649B2

公开(公告)日：2012-08-28

申请号：US12687694

申请日：2010-01-14

申请人： Yuri Hiraiwa ,  Yoshiyuki Nishi ,  Kenichi Oyamada ,  Yoshinori Matsui

发明人： Yuri Hiraiwa ,  Yoshiyuki Nishi ,  Kenichi Oyamada ,  Yoshinori Matsui

IPC分类号： G06F12/16

CPC分类号： G06F11/2058 ,  G06F11/2069 ,  G06F11/2076 ,  G06F11/2079 ,  G06F11/2082

摘要： The present invention causes an asynchronous remote copy to work together with storage clustering technology. A host computer program for controlling the asynchronous remote copy carries out an asynchronous remote copy pair operation by asynchronously working together with a switchover instruction of a storage clustering control program that performs a host write-destination volume switchover in a storage clustering environment.

摘要翻译： 本发明使异步远程副本与存储集群技术一起工作。 用于控制异步远程复制的主计算机程序通过与在存储集群环境中执行主机写目标卷切换的存储集群控制程序的切换指令异步地一起执行异步远程拷贝对操作。

公开(公告)号：US20120072687A1

公开(公告)日：2012-03-22

申请号：US13055447

申请日：2010-10-08

申请人： Yuri Hiraiwa ,  Yoshinori Matsui ,  Tetsuya Kaminaka ,  Kenichi Oyamada

发明人： Yuri Hiraiwa ,  Yoshinori Matsui ,  Tetsuya Kaminaka ,  Kenichi Oyamada

IPC分类号： G06F12/16 ,  G06F12/02

CPC分类号： G06F11/2056 ,  G06F3/0619 ,  G06F3/065 ,  G06F3/0689 ,  G06F11/1484

摘要： A computer system in an embodiment comprises a storage apparatus, a host computer, and a copy control program. The storage apparatus performs copy operations of volumes allocated to a guest OS of the host computer. The copy control program obtains volume information of the guest OS from a VM control program at a given time. The control program compares the information with previous volume information of the guest OS and performs volume copy control for the guest OS in accordance with the comparison result. This process achieve appropriate copy operations even if the association relationship between the guest OS and volumes is changed during system operation.

摘要翻译： 实施例中的计算机系统包括存储装置，主计算机和复制控制程序。 存储装置执行分配给主计算机的客户OS的卷的复制操作。 复制控制程序在给定时间从VM控制程序获取访客操作系统的卷信息。 控制程序将信息与客户操作系统的先前卷信息进行比较，并根据比较结果对客户操作系统执行卷复制控制。 即使在系统操作期间客户操作系统和卷之间的关联关系发生变化，此过程也会实现适当的复制操作。

公开(公告)号：US07965531B2

公开(公告)日：2011-06-21

申请号：US12435168

申请日：2009-05-04

申请人： Yoshinori Matsui ,  Toshio Sugano ,  Hiroaki Ikeda

发明人： Yoshinori Matsui ,  Toshio Sugano ,  Hiroaki Ikeda

IPC分类号： G11C5/02

CPC分类号： G11C11/408 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1063 ,  G11C8/12 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/0401

摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

摘要翻译： 在包括以预定数据宽度和传送速率发送/接收系统数据信号的多个DRAM芯片的存储器模块中，并且发送/接收具有较大数据宽度和较低传输速率的内部数据信号与 系统数据信号，系统数据信号的传输速率受到限制。 构成存储器模块的DRAM的电流消耗大，阻碍速度增加。 对于该存储器模块，多个DRAM芯片堆叠在IO芯片上。 每个DRAM芯片通过贯通电极连接到IO芯片，并且包括用于通过IO芯片相互转换每个DRAM芯片中的系统数据信号和内部数据信号的结构。 因此，可以缩短DRAM芯片之间的布线，并且可以仅在IO芯片上设置具有大电流消耗的DLL。

公开(公告)号：US07864618B2

公开(公告)日：2011-01-04

申请号：US12137802

申请日：2008-06-12

申请人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

发明人： Yoshiro Riho ,  Hayato Oishi ,  Yoshinori Haraguchi ,  Yoshinori Matsui

IPC分类号： G11C8/00

CPC分类号： G11C5/025 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48

摘要： A semiconductor memory device includes a plurality of banks, each of which is constituted of a plurality of memory cell arrays that are aligned in series in the longitudinal direction, wherein each memory cell array includes a plurality of memory cells, and wherein memory cell arrays of banks are collectively aggregated into a plurality of blocks, each of which includes memory cell arrays aligned in the perpendicular direction, in connection with a plurality of DQ pads. DQ pads are arranged in proximity to blocks. Substantially the same distance is set between memory cells and DQ pads so as to reduce dispersions in access times with respect to all DQ pads, thus achieving high-speed access in the semiconductor memory device. The wiring region of IO lines is reduced in the center area of the chip.

摘要翻译： 半导体存储器件包括多个存储体，每个存储体由在纵向方向上串联排列的多个存储单元阵列构成，其中每个存储单元阵列包括多个存储单元，并且其中存储单元阵列 银行被集体地聚集成多个块，每个块包括与多个DQ焊盘相关联的在垂直方向上排列的存储单元阵列。 DQ垫布置在块附近。 在存储单元和DQ垫之间基本上设置相同的距离，以便相对于所有DQ焊盘减少访问时间的分散，从而实现半导体存储器件中的高速访问。 在芯片的中心区域，IO线的布线区域减小。

公开(公告)号：US07756205B2

公开(公告)日：2010-07-13

申请号：US11660750

申请日：2005-08-30

申请人： Tadamasa Toma ,  Shinya Kadono ,  Masayasu Iguchi ,  Tomoyuki Okada ,  Yoshinori Matsui ,  Satoshi Kondo ,  Hiroshi Yahata ,  Wataru Ikeda

发明人： Tadamasa Toma ,  Shinya Kadono ,  Masayasu Iguchi ,  Tomoyuki Okada ,  Yoshinori Matsui ,  Satoshi Kondo ,  Hiroshi Yahata ,  Wataru Ikeda

IPC分类号： H04N7/12 ,  H04N11/02 ,  H04N11/04 ,  H04B1/66

CPC分类号： H04N9/8042 ,  G11B27/3027 ,  G11B27/329 ,  G11B2220/2541 ,  H04N5/85 ,  H04N9/8063 ,  H04N9/8205 ,  H04N9/8227 ,  H04N19/13 ,  H04N19/179 ,  H04N19/61

摘要： A moving image encoding method of encoding a moving image while switching between variable-length encoding schemes. In this method, a continuous unit to be continuously reproduced is determined (S5201), a stream is generated by encoding the moving image without switching between variable-length encoding schemes in the continuous unit (S5202), and management information is generated that includes a first flag information indicating that a variable-length encoding scheme is fixed in the continuous unit (S5204, and S5205).

摘要翻译： 一种在可变长度编码方案之间切换的同时对运动图像进行编码的运动图像编码方法。 在该方法中，确定要连续重放的连续单元（S5201），通过对运动图像进行编码而不在连续单元中的可变长度编码方案之间进行切换来生成流（S5202），生成包括 指示可变长度编码方案在连续单元中固定的第一标志信息（S5204和S5205）。

公开(公告)号：US20090182914A1

公开(公告)日：2009-07-16

申请号：US12318731

申请日：2009-01-07

申请人： Yoshinori Matsui

发明人： Yoshinori Matsui

IPC分类号： G06F12/02 ,  G06F13/16

CPC分类号： G11C7/1075

摘要： A semiconductor device that includes a plurality of memory cell arrays, a plurality of ports, a plurality of internal address generating circuits, and a controller. The plurality of internal address generating circuits may generate first and second internal addresses of first and second memory cell arrays of the plurality of memory cell arrays. The first internal address may designate a first area of the first memory cell array. The second internal address may designate a second area of the second memory cell array. The controller reads a series of data from the first area sequentially and writes the series of read data into the second area sequentially without transferring the series of read data to the plurality of ports.

摘要翻译： 一种半导体器件，包括多个存储单元阵列，多个端口，多个内部地址生成电路和控制器。 多个内部地址产生电路可以生成多个存储单元阵列中的第一和第二存储单元阵列的第一和第二内部地址。 第一内部地址可以指定第一存储单元阵列的第一区域。 第二内部地址可以指定第二存储单元阵列的第二区域。 控制器顺序地从第一区域读取一系列数据，并将读取数据序列顺序地写入第二区域，而不将该系列读取数据传送到多个端口。

公开(公告)号：US07548444B2

公开(公告)日：2009-06-16

申请号：US12003707

申请日：2007-12-31

申请人： Yoshinori Matsui ,  Toshio Sugano ,  Hiroaki Ikeda

发明人： Yoshinori Matsui ,  Toshio Sugano ,  Hiroaki Ikeda

IPC分类号： G11C5/02

CPC分类号： G11C11/408 ,  G11C5/00 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1051 ,  G11C7/1063 ,  G11C8/12 ,  G11C29/1201 ,  G11C29/26 ,  G11C29/48 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/0401

摘要： In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

摘要翻译： 在包括以预定数据宽度和传送速率发送/接收系统数据信号的多个DRAM芯片的存储器模块中，并且发送/接收具有较大数据宽度和较低传送速率的内部数据信号与 系统数据信号，系统数据信号的传输速率受到限制。 构成存储器模块的DRAM的电流消耗大，阻碍速度增加。 对于该存储器模块，多个DRAM芯片堆叠在IO芯片上。 每个DRAM芯片通过贯通电极连接到IO芯片，并且包括用于通过IO芯片相互转换每个DRAM芯片中的系统数据信号和内部数据信号的结构。 因此，可以缩短DRAM芯片之间的布线，并且可以仅在IO芯片上设置具有大电流消耗的DLL。

公开(公告)号：US07515496B2

公开(公告)日：2009-04-07

申请号：US11984352

申请日：2007-11-16

申请人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

发明人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40615

摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.

摘要翻译： 一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。

公开(公告)号：US07436859B2

公开(公告)日：2008-10-14

申请号：US10504295

申请日：2003-04-22

申请人： Youji Notoya ,  Yoshinori Matsui ,  Tadamasa Toma ,  Koji Imura ,  Naoto Otake

发明人： Youji Notoya ,  Yoshinori Matsui ,  Tadamasa Toma ,  Koji Imura ,  Naoto Otake

IPC分类号： H04J3/04

CPC分类号： H04N21/85406 ,  H04N21/434

摘要： A demultiplexing apparatus includes a data obtainment unit to obtain the MP4 file data, and a decoding unit to demultiplex the MP4 file data obtained by the data obtainment unit into pairs of a moov and a mdat and pairs of a moof and a mdat, and decode those pairs pair-by-pair. A content duration specification unit specifies the content total duration based on the content total duration information contained in the moov of the MP4 file data obtained by the data obtainment unit and a playback unit displays the content total duration specified by the content duration specification unit.

摘要翻译： 解复用装置包括获取MP4文件数据的数据获取单元，以及解码单元，用于将由数据获取单元获取的MP4文件数据解复用成moov和mdat以及moof和mdat对，并将其解码 那对配对。 内容持续时间指定单元基于由数据获取单元获得的MP4文件数据的moov中包含的内容总持续时间信息来指定内容总持续时间，并且重放单元显示由内容持续时间指定单元指定的内容总持续时间。

公开(公告)号：US07307909B2

公开(公告)日：2007-12-11

申请号：US11297646

申请日：2005-12-09

申请人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

发明人： Yoshinori Matsui ,  Hitoshi Tanaka ,  Kazuhiko Kajigaya ,  Akiyoshi Yamamoto ,  Tadashi Onodera

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C11/40615

摘要： A self-refresh timer circuit for generating a timer period for controlling self-refresh operation of a semiconductor memory device comprising: a temperature-dependent voltage source for outputting a voltage having a temperature dependency based on a diode characteristic; a control current generating circuit for applying an output voltage of the temperature-dependent voltage source to a temperature detecting device having a diode characteristic and for generating a control current having a magnitude in proportion to a current flowing through the temperature detecting device; and a timer period generating circuit for generating a timer period in inverse proportion to the magnitude of the control current.

摘要翻译： 一种自刷新定时器电路，用于产生用于控制半导体存储器件的自刷新操作的定时器周期，包括：用于输出基于二极管特性的具有温度依赖性的电压的温度相关电压源; 控制电流产生电路，用于将温度依赖电压源的输出电压施加到具有二极管特性的温度检测装置，并产生与流过温度检测装置的电流成比例的控制电流; 以及定时器周期发生电路，用于产生与控制电流的大小成反比的定时器周期。