公开(公告)号：US4808444A

公开(公告)日：1989-02-28

申请号：US99854

申请日：1987-09-22

申请人： Takeshi Yamazaki ,  Nobuyuki Yoshida ,  Yasuhiro Iizuka

发明人： Takeshi Yamazaki ,  Nobuyuki Yoshida ,  Yasuhiro Iizuka

IPC分类号： B05C5/02 ,  B05C5/00 ,  B05C9/06 ,  B05D1/26 ,  G03C1/74 ,  B05D1/30 ,  B05D1/34

CPC分类号： B05D1/26 ,  B05C5/007 ,  G03C1/74 ,  B05C9/06 ,  G03C2001/7418

摘要： A coating method and apparatus in which a coating composition is applied from a hopper to a web continuously travelling on a backing roller. The backing roller is rapidly moved by a pneumatic mechanism relative to the hopper between positions at which the composition can and cannot be applied to the travelling web in order to avoid thick coating at a leading portion or at a spliced portion of the web.

公开(公告)号：US4636474A

公开(公告)日：1987-01-13

申请号：US573315

申请日：1984-01-24

申请人： Kenji Ogura ,  Takeshi Yamazaki

发明人： Kenji Ogura ,  Takeshi Yamazaki

IPC分类号： A61B10/00 ,  E03D9/00 ,  C12M1/34

CPC分类号： A61B10/0038 ,  E03D9/00

摘要： A toilet apparatus is provided in a lavatory having at least one stool, urinal, bidet, or similar toilet structure. The toilet apparatus comprises a detecting sensor for detecting constituents in the feces, urine, or both of a user, and an indicator for indicating or informing the user of his health based upon abnormalities in the constituents detected by the sensor. The apparatus is particularly useful in informing the user of a toilet of his health each time he uses the toilet.

摘要翻译： 在具有至少一个粪便，小便池，坐浴盆或类似的厕所结构的厕所中设置有卫生间装置。 厕所装置包括用于检测用户的粪便，尿液或两者中的成分的检测传感器，以及用于基于由传感器检测到的成分的异常来指示或通知用户健康的指示器。 该装置特别有用于在每次使用马桶时通知使用者他的健康。

公开(公告)号：US08321866B2

公开(公告)日：2012-11-27

申请号：US13206968

申请日：2011-08-10

申请人： Masakazu Suzuoki ,  Takeshi Yamazaki

发明人： Masakazu Suzuoki ,  Takeshi Yamazaki

IPC分类号： G06F9/46

CPC分类号： G06F12/1466 ,  H04L69/12

摘要： A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A processing system for processing computer tasks is also provided. A first processor is of a first processor type and a number of second processors are of a second processor type. One of the second processors manages process scheduling of computing tasks by providing tasks to at least one of the first and second processors.

摘要翻译： 提供了一种用于宽带网络高速处理的计算机体系结构和编程模型。 该架构采用一致的模块化结构，通用的计算模块和统一的软件单元。 公共计算模块包括控制处理器，多个处理单元，处理单元处理程序的多个本地存储器，直接存储器存取控制器和共享主存储器。 还提供了一种用于由处理单元协调地读取和从共享主存储器写入数据的同步系统和方法。 还提供了一种用于处理计算机任务的处理系统。 第一处理器是第一处理器类型，并且多个第二处理器是第二处理器类型。 第二处理器之一通过向第一和第二处理器中的至少一个提供任务来管理计算任务的进程调度。

公开(公告)号：US08260072B2

公开(公告)日：2012-09-04

申请号：US12533157

申请日：2009-07-31

申请人： Hiroshi Kajiwara ,  Takeshi Yamazaki

发明人： Hiroshi Kajiwara ,  Takeshi Yamazaki

IPC分类号： G06K9/36

CPC分类号： H04N19/194 ,  H04N19/124 ,  H04N19/13 ,  H04N19/152 ,  H04N19/176 ,  H04N19/18

摘要： This invention provides a technique of easily encoding image data to generate encoded data having high image quality within a target code amount using a small memory capacity by image encoding processing of performing frequency transform and quantization of each pixel block. A frequency transform unit separates image data into low frequency band data and high frequency band data. A coefficient quantizing unit, coefficient encoder, and code amount controller operate to encode the high frequency band data within a predetermined amount. When the encoding processing of the high frequency band data has ended, the quantization parameter of the low frequency band data is set based on the generated code amount of the high frequency band data. A coefficient quantizing unit, coefficient encoder, code amount detector, and quantization parameter updating unit operate to encode the low frequency band data into codes within a low frequency band target code amount.

摘要翻译： 本发明提供一种技术，通过对每个像素块执行频率变换和量化的图像编码处理，通过使用小的存储容量来容易地编码图像数据以产生具有目标代码量内的高图像质量的编码数据。 频率变换单元将图像数据分离成低频带数据和高频带数据。 系数量化单元，系数编码器和代码量控制器操作以在预定量内对高频带数据进行编码。 当高频带数据的编码处理结束时，基于高频带数据的生成代码量来设定低频带数据的量化参数。 系数量化单元，系数编码器，代码量检测器和量化参数更新单元用于将低频带数据编码成低频带目标代码量内的代码。

公开(公告)号：US08218648B2

公开(公告)日：2012-07-10

申请号：US12412002

申请日：2009-03-26

申请人： Hiroki Kishi ,  Takeshi Yamazaki

发明人： Hiroki Kishi ,  Takeshi Yamazaki

IPC分类号： H04N11/02 ,  G06K9/36

CPC分类号： H04N19/59 ,  H04N19/124 ,  H04N19/18 ,  H04N19/48 ,  H04N19/593

摘要： This invention enables to generate encoded data without noticeable image quality degradation when reproducing an image at a lower resolution not to mention the original resolution. To accomplish this, when setting is done to transmit an image captured by a digital camera to a network, code stream forming information CF is set to “2” to arrange the encoded data of each tile in a resolution order. To suppress image quality degradation when reproducing at an intermediate resolution, stream conversion information SC is set to “2”. When encoding image data in compression processing, block overlap processing of suppressing discontinuity of data at the boundary between adjacent blocks is executed as many times as the count set in the stream conversion information. The obtained encoded data is arranged in accordance with the code stream forming information CF and output.

摘要翻译： 当以更低分辨率再现图像时，本发明能够生成编码数据，而不会引起图像质量下降，而不是提及原始分辨率。 为了实现这一点，当完成设置以将由数字照相机捕获的图像发送到网络时，代码流形成信息CF被设置为“2”，以按照分辨率顺序排列每个瓦片的编码数据。 为了在以中间分辨率再现时抑制图像质量劣化，流转换信息SC被设置为“2”。 当在压缩处理中对图像数据进行编码时，执行抑制相邻块之间的边界处的数据不连续性的块重叠处理与流转换信息中设置的计数一样多的次数。 获得的编码数据根据码流形成信息CF进行排列并输出。

公开(公告)号：US07877523B2

公开(公告)日：2011-01-25

申请号：US12331733

申请日：2008-12-10

申请人： Matthew Edward King ,  Peichum Peter Liu ,  David Mui ,  Takeshi Yamazaki

发明人： Matthew Edward King ,  Peichum Peter Liu ,  David Mui ,  Takeshi Yamazaki

IPC分类号： G06F3/00 ,  G06F13/00

CPC分类号： G06F13/28

摘要： An apparatus and a computer program product are provided for completing a plurality of (direct memory access) DMA commands in a computer system. It is determined whether the DMA commands are chained together as a list DMA command. Upon a determination that the DMA commands are chained together as a list DMA command, it is also determined whether a current list element of the list DMA command is fenced. Upon a determination that the current list element is not fenced, a next list element is fetched and processed before the current list element has been completed.

摘要翻译： 提供了一种用于在计算机系统中完成多个（直接存储器访问）DMA命令的装置和计算机程序产品。 确定DMA命令是否作为列表DMA命令链接在一起。 在确定DMA命令被链接在一起作为列表DMA命令时，还确定列表DMA命令的当前列表元素是否被围栏。 当确定当前列表元素不被围栏时，在当前列表元素已经完成之前获取和处理下一个列表元素。

公开(公告)号：US07876013B2

公开(公告)日：2011-01-25

申请号：US12379668

申请日：2009-02-26

申请人： Masayuki Okubo ,  Satoru Negishi ,  Koji Nara ,  Takeshi Yamazaki

发明人： Masayuki Okubo ,  Satoru Negishi ,  Koji Nara ,  Takeshi Yamazaki

IPC分类号： H02K1/28

CPC分类号： H02K29/03 ,  H02K1/278 ,  H02K1/28 ,  H02K2201/06

摘要： A brushless motor has rotor cores dividedly formed as plural sections in an axial direction, segment magnets secured to outer circumferential surfaces of the rotor cores, and magnet holders secured to the rotor cores, respectively, for holding the segment magnet. Each of the rotor cores has holder-positioning grooves to which holder arms are fitted, and bridge parts formed corresponding to the holder positioning grooves. Each of the magnet holders has joint grooves fitted in the bridge parts and displaced from the holder arms by a step angle, the bridge parts being fitted in the joint grooves, thereby assembling a rotor.

摘要翻译： 无刷电动机具有沿轴向分割形成为多个部分的转子铁芯，分别固定在转子铁芯的外周面上的分段磁体和固定在转子铁芯上的用于保持分段磁铁的磁铁保持架。 每个转子芯具有保持器定位槽，保持器臂装配到该槽，以及对应于保持器定位槽形成的桥接部。 每个磁体保持器具有装配在桥接部分中的接合槽并且从保持器臂以一个阶梯角移位，桥接部分嵌入在接合槽中，从而组装转子。

公开(公告)号：US07802023B2

公开(公告)日：2010-09-21

申请号：US11250246

申请日：2005-10-14

申请人： Takeshi Yamazaki ,  Scott Douglas Clark ,  Charles Ray Johns ,  James Allan Kahle

发明人： Takeshi Yamazaki ,  Scott Douglas Clark ,  Charles Ray Johns ,  James Allan Kahle

IPC分类号： G06F3/00 ,  G06F13/42

CPC分类号： G06F12/0815 ,  G06F12/0835

摘要： Methods and apparatus provide for interconnecting one or more multiprocessors and one or more external devices through one or more configurable interface circuits, which are adapted for operation in: (i) a first mode to provide a coherent symmetric interface; or (ii) a second mode to provide a non-coherent interface.

摘要翻译： 方法和装置提供通过一个或多个可配置接口电路来互连一个或多个多处理器和一个或多个外部设备，其适于在以下操作中操作：（i）提供一致对称接口的第一模式; 或（ii）提供非相干界面的第二模式。

公开(公告)号：US07725618B2

公开(公告)日：2010-05-25

申请号：US10902474

申请日：2004-07-29

申请人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

发明人： Michael Norman Day ,  Charles Ray Johns ,  Peichun Peter Liu ,  Thuong Truong ,  Takeshi Yamazaki

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： The present invention provides a method and apparatus for creating memory barriers in a Direct Memory Access (DMA) device. A memory barrier command is received and a memory command is received. The memory command is executed based on the memory barrier command. A bus operation is initiated based on the memory barrier command. A bus operation acknowledgment is received based on the bus operation. The memory barrier command is executed based on the bus operation acknowledgment. In a particular aspect, memory barrier commands are direct memory access sync (dmasync) and direct memory access enforce in-order execution of input/output (dmaeieio) commands.

摘要翻译： 本发明提供了一种用于在直接存储器访问（DMA）设备中创建存储障碍的方法和装置。 接收到存储器屏障命令并接收存储器命令。 内存命令是根据内存屏障命令执行的。 基于内存障碍命令启动总线操作。 基于总线操作接收总线操作确认。 基于总线操作确认执行存储器障碍命令。 在特定方面，存储器屏障命令是直接存储器访问同步（dmasync），并且直接存储器访问强制执行输入/输出（dmaeie））命令的按顺序执行。

公开(公告)号：US20100058024A1

公开(公告)日：2010-03-04

申请号：US12550936

申请日：2009-08-31

申请人： Yuji Kawamura ,  Takeshi Yamazaki

发明人： Yuji Kawamura ,  Takeshi Yamazaki

IPC分类号： G06F12/02

CPC分类号： G06F12/084 ,  G06F9/3824 ,  G06F9/3885

摘要： A processor includes a CPU core which executes a user program, and a data transfer apparatus. The CPU core stores a transfer request from a user program in a specific area of a main memory, in which the transfer request specifies the virtual addresses of a transfer source and a transfer destination in a memory space allocated to the user program. The data transfer apparatus refers to the specific area of the main memory and acquires a transfer request asynchronously to processing performed by the CPU core. The data transfer apparatus then identifies physical addresses corresponding to virtual addresses specified in the transfer request. After that, the data transfer apparatus transcribes original data stored in a storage area indicated by the physical address of the transfer source, to a storage area in a cache memory related to the virtual address or physical address of the transfer destination.

摘要翻译： 处理器包括执行用户程序的CPU核心和数据传送装置。 CPU核存储来自主存储器的特定区域中的用户程序的传送请求，其中传送请求在分配给用户程序的存储空间中指定传送源和传送目的地的虚拟地址。 数据传送装置是指主存储器的特定区域，并且与CPU核心执行的处理异步地获取传送请求。 然后，数据传送装置识别与传送请求中指定的虚拟地址对应的物理地址。 之后，数据传送装置将存储在由传送源的物理地址指定的存储区域中的原始数据转录到与传送目的地的虚拟地址或物理地址相关的高速缓冲存储器中的存储区域。