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公开(公告)号:US20240078307A1
公开(公告)日:2024-03-07
申请号:US18261461
申请日:2021-06-14
Applicant: THE INDUSTRY & ACADEMIC COOPERATION IN CHUNGNAM NATIONAL UNIVERSITY , KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
Inventor: Jinsoo JANG , Brent Byunghoon KANG
Abstract: The present invention relates to an apparatus for reinforcing security of a mobile trusted execution environment, and relates to an apparatus for reinforcing security of a mobile trusted execution environment for constructing a general-purpose trusted execution environment. According to an embodiment of the present invention, a technology available for a general purpose in a mobile device operating on the basis of an ARM architecture has effects of configuring a trusted execution environment for guaranteeing safe execution of an application without depending on an existing commercial security technology, and of configuring a mobile trusted execution environment by using a write area execution prevention function and a debugging watchpoint, which are general-purpose hardware functions.
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公开(公告)号:US11922988B2
公开(公告)日:2024-03-05
申请号:US17674301
申请日:2022-02-17
Inventor: Yang-Kyu Choi , Myung-Su Kim
IPC: G11C11/24 , G11C11/404 , G11C11/4096
CPC classification number: G11C11/404 , G11C11/4096
Abstract: Disclosed are a DRAM device capable of storing charges for a long time and an operating method thereof. According to an embodiment, a DRAM device includes a channel region formed on a substrate, a gate insulating film region formed on the channel region, a floating gate region formed on the gate insulating film region, a transition layer region formed on the floating gate region, and a control gate region formed on the transition layer region and generating a potential difference with the floating gate region in response to a fact that a potential that is not less than a reference potential is applied and releasing at least one charge stored in the floating gate region or storing the at least one charge into the floating gate region, by generating a transition current due to the potential difference.
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公开(公告)号:US11906457B2
公开(公告)日:2024-02-20
申请号:US17403389
申请日:2021-08-16
Inventor: Seokwoo Jeon , Donghwi Cho , Youngsuk Shim
CPC classification number: G01N27/128 , G01N27/125 , G01N33/0027
Abstract: A gas sensor includes a first electrode disposed on a substrate, a second electrode disposed on the substrate and spaced apart from the first electrode, and a sensitive member disposed on the substrate. The sensitive member contacts first and second electrodes and has a porous structure from a three-dimensional (3D) arrangement of shells including a gas-sensitive material. A thickness of the sensitive member is 5 μm to 10 μm, and a thickness of the shells is 10 nm to 40 nm.
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公开(公告)号:US11900607B2
公开(公告)日:2024-02-13
申请号:US17743448
申请日:2022-05-13
Inventor: Junyong Noh , Jung Eun Yoo , Kwanggyoon Seo , Sanghun Park , Jaedong Kim , Dawon Lee
CPC classification number: G06T7/11 , G06T7/62 , G06T15/205
Abstract: Provided is a method of framing a three dimensional (3D) target object for generation of a virtual camera layout. The method may include analyzing a reference video image to extract a framing rule for at least one reference object in the reference video image, generating a framing rule for at least one 3D target object using the framing rule for the at least one reference object in the reference video image, and using the framing rule for the at least one 3D target object for generation of a virtual camera layout.
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公开(公告)号:US20240047600A1
公开(公告)日:2024-02-08
申请号:US17630463
申请日:2021-12-15
Inventor: Yang-Kyu CHOI , Joon-Kyu HAN
IPC: H01L31/113 , G06N3/067
CPC classification number: H01L31/1136 , G06N3/067
Abstract: A transistor for implementing a photo-responsive neuronal device is disclosed. According to one example embodiment, the transistor includes a semiconductor substrate including a hole barrier region or an electron barrier region; a floating body extended in a horizontal direction on the hole barrier region or the electron barrier region; a source region and a drain region formed at both ends of the floating body; a gate insulating film formed on the floating body; and a gate region formed on the gate insulating film.
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公开(公告)号:US11895218B2
公开(公告)日:2024-02-06
申请号:US17720257
申请日:2022-04-13
Inventor: Jaehyouk Choi , Suneui Park , Seyeon Yoo , Seojin Choi , Jooeun Bang
Abstract: Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal SREF and a fundamental sampling phase detector (FSPD) configured to receive an output signal SILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).
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公开(公告)号:US11893704B2
公开(公告)日:2024-02-06
申请号:US17429254
申请日:2019-02-21
Inventor: Junyong Noh , Hanui Lee , Bumki Kim , Gukho Kim , Julie Alfonsine E. Lelong , Mohammad Reza Karimi Dastjerdi , Allen Kim , Jiwon Lee
CPC classification number: G06T3/20 , G06F18/22 , G06F18/253 , G06T7/11 , G06T7/74 , G06V10/443 , G06V10/62 , G06V10/751 , G06T2207/10016 , G06T2207/10024 , G06T2207/20092 , G06T2207/20221
Abstract: An image processing device according to one embodiment estimates optical flow information, pixel by pixel, on the basis of a reference image and input images of consecutive frames, and estimates a term corresponding to temporal consistency between the frames of the input images. The image processing device determines a mesh on the basis of the term corresponding to temporal consistency and the optical flow information, and transforms the reference image on the basis of the mesh. The image processing device preforms image blending on the basis of the input image, the transformed reference image, and mask data.
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公开(公告)号:US20240033304A1
公开(公告)日:2024-02-01
申请号:US18258643
申请日:2021-12-28
Inventor: Heung Kyu Lee , Jaeho Kim
IPC: A61K35/74 , A61K39/395 , A61P35/00
CPC classification number: A61K35/74 , A61K39/3955 , A61P35/00 , A61K2035/11
Abstract: The composition of the present invention induces changes in the composition of gut microbiota, particularly changes in the composition of Desulfovibrionasaceae strains, in a high glucose diet environment, so it has no toxicity to the body and has excellent brain tumor inhibitory activity, and thus it can effectively prevent, improve or treat brain tumors. Furthermore, such changes in the composition of gut microbiota in a high glucose diet environment induces a synergistic effect with anticancer drugs, particularly immune checkpoint inhibitors, and thus it can ultimately contribute to improving the survival rate of brain tumor patients.
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公开(公告)号:US11887151B2
公开(公告)日:2024-01-30
申请号:US17671114
申请日:2022-02-14
Inventor: Sooel Son , Joon Gyum Kim
IPC: G06Q30/02 , G06Q30/0242 , G06F3/01 , G06Q30/0251 , G06Q30/0241
CPC classification number: G06Q30/0244 , G06F3/013 , G06Q30/0269 , G06Q30/0277
Abstract: The present disclosure in at least one embodiment provides a method of providing an advertisement disclosure for advertisement identification to a content that is displayed in a three-dimensional space by a visual interface, including detecting an advertisement object located within a user sight from the content, inserting the advertisement disclosure in an adjacent position to the advertisement object, and controlling the advertisement disclosure in position or orientation based on a user gaze upon detecting the user gaze.
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公开(公告)号:US20240028297A1
公开(公告)日:2024-01-25
申请号:US18148161
申请日:2022-12-29
Inventor: Kyunghyun KIM , Seonghwan CHO
CPC classification number: G06F7/5443 , G06N3/063
Abstract: A semiconductor device includes a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; and a computing circuit configured to perform a multiplication and accumulation (MAC) operation using a plurality of input data and a plurality of weights respectively provided from the plurality of bit lines, wherein one or more memory cells connected to each of the plurality of bit lines store a corresponding one of the plurality of weights, and the one or more memory cells store sign information of the corresponding weight.
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