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公开(公告)号：US20230155696A1
公开(公告)日：2023-05-18
申请号：US17983142
申请日：2022-11-08
发明人： MENG-CHE LI , CHIEN-JUNG HUANG
摘要： A calibration circuit and a calibration method for a wireless transceiver are provided. The wireless transceiver includes a transmission path and a reception path, and the transmission path includes a radio frequency (RF) circuit and a baseband amplifier. The calibration method includes the following steps: setting a target gain of the RF circuit according to a first gain setting value; receiving a first input signal through a coupling path and the reception path; measuring first power of the first input signal; setting the target gain of the RF circuit according to a second gain setting value; receiving a second input signal through the coupling path and the reception path; measuring second power of the second input signal; calculating a power difference between the first power and the second power; and adjusting at least one of the baseband amplifier and a digital circuit according to the power difference.
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公开(公告)号：US20230154524A1
公开(公告)日：2023-05-18
申请号：US17528208
申请日：2021-11-17
发明人： KUO-WEI CHI , CHUN-CHI YU , CHIH-WEI CHANG , GER-CHIH CHOU
IPC分类号： G11C11/4076
CPC分类号： G11C11/4076
摘要： Disclosed is a DDR SDRAM signal calibration device capable of adapting to the variation of voltage and/or temperature. The device includes: an enablement signal setting circuit configured to generate data strobe (DQS) enablement setting; a signal gating circuit configured to generate a DQS enablement setting signal and a DQS enablement signal according to the DQS enablement setting and then output a gated DQS signal according to the DQS enablement signal and a DQS signal; and a calibration circuit configured to generate a first delay signal according to the DQS enablement setting signal and generate a second delay signal according to the first delay signal, the calibration circuit further configured to generate a calibration signal according to the first and second delay signals and the DQS signal. The enablement signal setting circuit maintains or adjusts the DQS enablement setting according to the calibration signal.
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公开(公告)号：US20230144972A1
公开(公告)日：2023-05-11
申请号：US17933853
申请日：2022-09-21
发明人： Cheng-Wei LUO , Hsiao-Tsung YEN
CPC分类号： H01F17/0013 , H01F17/02 , H01F2017/0073 , H01F2017/004
摘要： An inductor device is disclosed herein. An electrical device is disposed in a first area of the inductor device, and the inductor device includes a first trace and a second trace. The first trace is disposed in a second area. The second trace is disposed in the second area, and coupled to the first trace. The second area is disposed an outer side of the first area, and the first area and the second area are not overlapped with each other.
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公开(公告)号：US20230143824A1
公开(公告)日：2023-05-11
申请号：US17870983
申请日：2022-07-22
发明人： SHIH-HSIUNG HUANG
CPC分类号： H03M1/1215 , H03M1/1245 , H03M1/38
摘要： A time-interleaved analog to digital converter includes coarse converter circuitries, a control logic circuit, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The coarse converter circuitries sequentially sample an input signal and perform coarse conversions to generate decision signals. The control logic circuit generates coarse digital codes according to the decision signals. The first and second transfer circuits respectively transfer first and second residue signals. The fine converter circuitry performs a fine conversion according to a corresponding first residue signal and a corresponding second residue signal to generate a fine digital code. A sampling interval for sampling the input signal and a coarse conversion interval for performing the coarse conversion are determined based on a fine conversion interval for performing the fine conversion. The encoder circuit generates a digital output according to a corresponding coarse digital code and the fine digital code.
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公开(公告)号：US20230137324A1
公开(公告)日：2023-05-04
申请号：US17865720
申请日：2022-07-15
发明人： I-HAO CHIANG
IPC分类号： G11C15/04
摘要： A content addressable memory cell includes storage circuits and a comparator circuit. A first storage circuit of the storage circuits is configured to store data, and a second storage circuit of the storage circuits is configured to store a state bit. The comparator circuit is configured to determine whether to adjust a level of a match line to a level of one of the data and the state bit in response to levels of search bit lines and another one of the data and the state bit.
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公开(公告)号：US20230136927A1
公开(公告)日：2023-05-04
申请号：US17973706
申请日：2022-10-26
发明人： YAO-CHIA LIU , YUAN-SHENG LEE
IPC分类号： H03K5/135 , H03K5/15 , H03K19/173
摘要： A quadrant alternate switching phase interpolator includes first and second multiplexer circuits, a phase interpolator circuitry, and a controller circuitry. The first multiplexer circuit outputs one of first and second clock signals to be a first signal in response to first and third bits in a quadrant control code. The second multiplexer circuit outputs one of third and fourth clock signals to be a second signal in response to second and fourth bits in the quadrant control code, and the first, the third, the second, and fourth clock signals are sequentially different in phase by 90 degrees. The phase interpolator circuitry generates an output clock signal in response to the first and the second signals and phase control bits. The controller circuitry performs a bit-shift operation on the phase control bits to adjust a phase of the output clock signal.
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公开(公告)号：US20230135496A1
公开(公告)日：2023-05-04
申请号：US18048201
申请日：2022-10-20
发明人： CHIA HAN LIN , MENG AN KUO , ZONG-DA HUANG
IPC分类号： G01R31/28
摘要： A test method is configured to test a chip on a circuit under test, wherein the circuit under test further includes a DC-DC converter. The test method includes the operations of: generating a test pulse signal; filtering the test pulse signal to generate a first test DC voltage to the DC-DC converter, wherein the DC-DC converter transforms the first test DC voltage to a second test DC voltage and transmits the second test DC voltage to the chip; and extracting an output signal of the chip to determine a performance of the chip, wherein the chip generates the output signal according to the second test DC voltage.
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公开(公告)号：US11631517B2
公开(公告)日：2023-04-18
申请号：US16155058
申请日：2018-10-09
发明人： Hsiao-Tsung Yen , Yuh-Sheng Jean , Ta-Hsun Yeh
摘要： An 8-shaped inductive coil device that includes a first and a second spiral coils and a connection segment structure is provided. The first spiral coil includes first metal segments and crossing connection segments disposed at a first and a second metal layers respectively and includes first connection terminals. The second spiral coil includes second connection terminals. The connection segment structure electrically couples the first and the second connection terminals. The first and the second spiral coils are disposed along an imaginary line passing through a central region of each of ranges surrounded by the first and the second spiral coils. The connection segment structure and the crossing connection segments electrically couple the part of the first metal segments substantially vertical to the imaginary line, and the connection segment structure and the crossing connection segments are disposed substantially on the imaginary line.
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99.发明申请公开(公告)号：US20230115471A1
公开(公告)日：2023-04-13
申请号：US17857621
申请日：2022-07-05
发明人： SHIH-HSIUNG HUANG , WEI-CIAN HONG , SHENG-YEN SHIH
摘要： A successive approximation register analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, and a control logic circuitry. The charge injection DAC circuit includes capacitors that sample input signals to generate first and second signals and charge injection circuits that selectively adjust the first or the second signals according to enable signals and decision signals. The comparator circuit compares the first and second signals to generate the decision signals. The control logic circuitry controls a circuit of the charge injection circuits to adjust the first and the second signals during an initial phase, in order to adjust a switching sequence of the circuit according to the decision signals corresponding to the initial phase, and generates the enable signals according to the decision signals and the adjusted switching sequence during a conversion phase to generate a digital output.
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公开(公告)号：US20230102504A1
公开(公告)日：2023-03-30
申请号：US17950576
申请日：2022-09-22
发明人： LIANG-HUI LI , YU-CHANG CHEN , MING-CHIH KUAN
摘要： A photoplethysmography front-end receiver is capable of eliminating an error in the estimation of an ambient-light current. The receiver includes a current-to-voltage conversion circuit, an integrator, a switch circuit, and an analog-to-digital converter (ADC). The current-to-voltage conversion circuit converts an input current into a differential voltage signal. The integrator receives the differential voltage signal and outputs an analog output voltage. The switch circuit is set between the current-to-voltage conversion circuit and the integrator, forwards the differential voltage signal to the integrator in a first duration when a controllable light source is turned on, and forwards an inverted signal of the differential voltage signal to the integrator in a second duration when the controllable light source is turned off, wherein the second duration is after or before the first duration. The ADC generates a digital signal for analysis according to the analog output voltage after the second duration.
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