利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

23829 条记录 (耗时 0.066 秒)

    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
    91.
    发明申请
    SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF 有权

    公开(公告)号：US20230067587A1

    公开(公告)日：2023-03-02

    申请号：US17460200

    申请日：2021-08-28

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

    IPC分类号： H01L27/06 ,  H01L27/092 ,  H01L29/66 ,  H01L29/423 ,  H01L29/40 ,  H01L21/8238

    摘要： A semiconductor device includes a semiconductor substrate. The semiconductor device includes a first three-dimensional semiconductor structure of a first conductivity type protruding from a surface of the semiconductor substrate. The semiconductor device includes a second three-dimensional semiconductor structure of a second conductivity type protruding from the surface of the semiconductor substrate. The semiconductor device includes a first transistor having a first source/drain structure formed in the first three-dimensional semiconductor structure, a second source/drain structure formed in the second three-dimensional semiconductor structure, a first gate structure straddling a first portion of the first three-dimensional semiconductor structure and a first portion of the second three-dimensional semiconductor structure, and a second gate structure straddling a second portion of the second three-dimensional semiconductor structure.

    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    94.
    发明申请
    SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20230067299A1

    公开(公告)日：2023-03-02

    申请号：US17461308

    申请日：2021-08-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： MING CHYI LIU ,  CHUN-TSUNG KUO

    IPC分类号： H01L49/02

    摘要： A semiconductor structure includes a substrate, at least one dielectric layer and a capacitor structure. The at least one dielectric layer is disposed over the substrate, and the at least one dielectric layer includes a step edge profile. The capacitor structure is disposed over the substrate. The capacitor structure includes a bottom electrode, a capacitor dielectric layer and a top electrode. The bottom electrode covers the step edge profile of the at least one dielectric layer and has a first step profile substantially conformal to the step edge profile of the at least one dielectric layer. The capacitor dielectric layer covers the bottom electrode and has a second step profile substantially conformal to the first step profile. The top electrode covers the capacitor dielectric layer.

    SEMICONDUCTOR STRUCTURE
    95.
    发明申请
    SEMICONDUCTOR STRUCTURE 有权

    公开(公告)号：US20230067210A1

    公开(公告)日：2023-03-02

    申请号：US17463507

    申请日：2021-08-31

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

    发明人： HSING-I TSAI ,  FU-HUAN TSAI ,  CHIA-CHUNG CHEN ,  HSIAO-CHUN LEE ,  CHI-FENG HUANG ,  CHO-YING LU ,  VICTOR CHIANG LIANG

    IPC分类号： H01L29/08 ,  H01L29/06

    摘要： A semiconductor structure includes a gate structure, a source region, a drain region, and an isolation structure. The gate structure includes a first portion, a second portion and a third portion. The first portion extends in a first direction, and the second portion and the third portion extend in a second direction. The second portion and the third portion are disposed at opposite ends of the first portion. The source region and the drain region are separated by the gate structure. The isolation structure surrounds the gate structure, the source region and the drain region. The first portion has a first sidewall, the second portion has a second sidewall, and the third portion has a third sidewall. The first sidewall, the second sidewall and the third sidewall are parallel to the first direction and aligned with each other to form a straight line.

    BIT CELL WITH BACK-SIDE METAL LINE DEVICE AND METHOD
    96.
    发明申请
    BIT CELL WITH BACK-SIDE METAL LINE DEVICE AND METHOD 有权

    公开(公告)号：US20230067140A1

    公开(公告)日：2023-03-02

    申请号：US17463172

    申请日：2021-08-31

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Chien-Ying CHEN ,  Yao-Jen YANG

    IPC分类号： H01L27/112 ,  G06F30/392

    摘要： A one-time programmable (OTP) bit cell includes a substrate including a front side and a back side, an active area on the front side, a first read transistor including a first gate and a first portion of the active area intersected by the first gate, a program transistor including a second gate and a second portion of the active area intersected by the second gate, a first electrical connection to the first gate, a second electrical connection to the second gate, and a third electrical connection to the active area. At least one of the first, second, or third electrical connections includes a metal line positioned on the back side.

    SEMICONDUCTOR DIE PACKAGE WITH RING STRUCTURE AND METHOD FOR FORMING THE SAME
    99.
    发明申请
    SEMICONDUCTOR DIE PACKAGE WITH RING STRUCTURE AND METHOD FOR FORMING THE SAME 有权

    公开(公告)号：US20230066752A1

    公开(公告)日：2023-03-02

    申请号：US17462505

    申请日：2021-08-31

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yu-Sheng LIN ,  Shu-Shen YEH ,  Chin-Hua WANG ,  Po-Yao LIN ,  Shin-Puu JENG

    IPC分类号： H01L21/56 ,  H01L23/31 ,  H01L23/58 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

    摘要： A semiconductor die package and a method of forming the same are provided. The semiconductor die package includes a package substrate, an interposer substrate over the package substrate, two semiconductor dies over the interposer substrate, and an underfill element formed over the interposer substrate and surrounding the semiconductor dies. A ring structure is disposed over the package substrate and surrounds the semiconductor dies. Recessed parts are recessed from the bottom surface of the ring structure. The recessed parts include multiple first recessed parts arranged in each corner area of the ring structure and two second recessed parts arranged in opposite side areas of the ring structure and aligned with a portion of the underfill element between the semiconductor dies. An adhesive layer is interposed between the bottom surface of the ring structure and the package substrate.