Memory and memory controller for high reliability operation and method
    92.
    发明授权
    Memory and memory controller for high reliability operation and method 有权
    内存和内存控制器,实现高可靠性操作和方法

    公开(公告)号:US09293188B2

    公开(公告)日:2016-03-22

    申请号:US14171362

    申请日:2014-02-03

    Inventor: Kevin M. Brandl

    Abstract: In one form, a memory includes a memory bank, a page buffer, and an access circuit. The memory bank has a plurality of rows and a plurality of columns with volatile memory cells at intersections of the plurality of row and the plurality of columns. The page buffer is coupled to the plurality of columns and stores contents of a selected one of the plurality of rows. The access circuit is responsive to an adjacent command and a row address to perform a predetermined operation on the row address, and to refresh first and second addresses adjacent to the row address. In another form, a memory controller is adapted to interface with such a memory to select either a normal command or an adjacent command based on a number of activate commands sent to the row in a predetermined time window.

    Abstract translation: 在一种形式中,存储器包括存储体,页面缓冲器和访问电路。 存储体具有在多行和多列的交叉处具有易失性存储单元的多行和多列。 页面缓冲器耦合到多个列,并且存储多行中所选择的一行的内容。 访问电路响应相邻命令和行地址来对行地址执行预定操作,并且刷新与行地址相邻的第一和第二地址。 在另一形式中,存储器控制器适于与这样的存储器接口,以基于在预定时间窗口中发送到行的激活命令的数量来选择正常命令或相邻命令。

    Data processor with memory controller for high reliability operation and method
    93.
    发明授权
    Data processor with memory controller for high reliability operation and method 有权
    具有内存控制器的数据处理器,实现高可靠性操作和方法

    公开(公告)号:US09281046B2

    公开(公告)日:2016-03-08

    申请号:US14048212

    申请日:2013-10-08

    Inventor: Kevin M. Brandl

    CPC classification number: G11C11/40603 G06F13/1605 G06F13/1642

    Abstract: A data processor includes a memory accessing agent and a memory controller. The memory accessing agent generates a plurality of accesses to a memory. The memory controller is coupled to the memory accessing agent and schedules the plurality of memory accesses in an order based on characteristics of the memory. The characteristics of the memory include a row cycle page time (tRCPAGE) indicative of an acceptable number of activate commands to a row in the memory within a predetermined time window.

    Abstract translation: 数据处理器包括存储器访问代理和存储器控制器。 存储器访问代理生成对存储器的多个访问。 存储器控制器耦合到存储器访问代理,并且基于存储器的特性按顺序调度多个存储器访问。 存储器的特性包括在预定时间窗口内指示存储器中的行的可接受数量的激活命令的行周期寻呼时间(tRCPAGE)。

    Data transfer device
    94.
    发明授权
    Data transfer device 有权
    数据传输设备

    公开(公告)号:US09262314B2

    公开(公告)日:2016-02-16

    申请号:US13968984

    申请日:2013-08-16

    Abstract: A data transfer device includes a FIFO memory and a control unit which obtains a data amount of the FIFO memory to control the FIFO memory and outputs a selection signal corresponding to the obtained data amount of the FIFO memory. An output data generation unit generates output data including either one of the second output data and an interpolation data selected based on the selection signal, and a first output data stored in a frame memory.

    Abstract translation: 数据传送装置包括FIFO存储器和控制单元,其获得FIFO存储器的数据量以控制FIFO存储器并输出与所获得的FIFO存储器的数据量对应的选择信号。 输出数据生成单元生成包括基于选择信号选择的第二输出数据和插值数据中的任一个的输出数据和存储在帧存储器中的第一输出数据。

    METHOD AND SYSTEM MAINTAINING QUALITY OF SERVICE (QOS) OF HOST COMMANDS IN MULTI-PORT, MULTI-FUNCTION PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) DEVICES
    95.
    发明申请
    METHOD AND SYSTEM MAINTAINING QUALITY OF SERVICE (QOS) OF HOST COMMANDS IN MULTI-PORT, MULTI-FUNCTION PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) DEVICES 有权
    方法和系统维护多端口多功能外围组件互连显式(PCIE)设备主机服务质量(QOS)

    公开(公告)号:US20160034415A1

    公开(公告)日:2016-02-04

    申请号:US14800750

    申请日:2015-07-16

    CPC classification number: G06F13/4282 G06F13/1642 G06F13/28

    Abstract: A method maintaining a fixed QoS for a PCIe device accessed by multiple hosts includes; receiving commands from the hosts in PCIe function queues of the PCIe device, fetching the commands from the PCIe function command queues, queuing the commands according to a command arbitration policy established for the PCIe device, storing the queued commands in an internal memory of the PCIe device, retrieving the queued commands from the internal memory in a sequence determined by applying a calculated QoS to at least one of the queued commands, and allocating PCIe device resources based on payload information corresponding to each one of the retrieved commands.

    Abstract translation: 保持由多个主机访问的PCIe设备的固定QoS的方法包括: 从PCIe设备的PCIe功能队列中的主机接收命令,从PCIe功能命令队列获取命令,根据为PCIe设备建立的命令仲裁策略排队命令,将排队的命令存储在PCIe的内部存储器中 设备,以通过将计算的QoS应用于至少一个排队的命令确定的顺序从内部存储器检索排队的命令,以及基于与所检索的命令中的每一个对应的有效载荷信息来分配PCIe设备资源。

    Adaptive Scheduling Queue Control For Memory Controllers Based Upon Page Hit Distance Determinations
    97.
    发明申请
    Adaptive Scheduling Queue Control For Memory Controllers Based Upon Page Hit Distance Determinations 有权
    基于页面命中距离确定的内存控制器的自适应调度队列控制

    公开(公告)号:US20150339245A1

    公开(公告)日:2015-11-26

    申请号:US14283780

    申请日:2014-05-21

    CPC classification number: G06F13/1626 G06F13/1642 G06F13/1673

    Abstract: Methods and systems are disclosed for adaptive scheduling queue control based upon page hit distance determinations. A threshold occupancy value is determined for a window of previous access requests to a memory and used to adaptively control a number of access requests stored in a scheduling queue buffer. For certain embodiments, a page hit distance (PHD) determination for each access request and historical page hit distance data is used to adjust the threshold occupancy value that determines the number (N) of access requests stored in the buffer prior to removing an access request and using it to access the memory. For each access request, the page hit distance represents the number of previously received access requests since the last access request to access the same page of memory. An average PHD can be determined over a number (M) of previous access requests and used to control the threshold occupancy value.

    Abstract translation: 公开了基于页面命中距离确定的自适应调度队列控制的方法和系统。 确定对存储器的先前访问请求的窗口的阈值占用值,并且用于自适应地控制存储在调度队列缓冲器中的多个访问请求。 对于某些实施例,使用针对每个访问请求和历史页面命中距离数据的页面命中距离(PHD)确定来调整阈值占用值,该阈值占用值在去除访问请求之前确定存储在缓冲器中的访问请求的数量(N) 并使用它访问内存。 对于每个访问请求,页面命中距离表示自上一次访问请求以来接收访问同一页内存的访问请求的次数。 平均PHD可以在先前的访问请求的数量(M)上确定并用于控制阈值占用值。

    INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, STORAGE MEDIUM STORING PROGRAM FOR CONTROLLING INFORMATION PROCESSING DEVICE, AND METHOD FOR CONTROLLING INFORMATION PROCESSING DEVICE
    99.
    发明申请
    INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING SYSTEM, STORAGE MEDIUM STORING PROGRAM FOR CONTROLLING INFORMATION PROCESSING DEVICE, AND METHOD FOR CONTROLLING INFORMATION PROCESSING DEVICE 有权
    信息处理装置,信息处理系统,用于控制信息处理装置的存储媒体存储程序和用于控制信息处理装置的方法

    公开(公告)号:US20150278127A1

    公开(公告)日:2015-10-01

    申请号:US14618044

    申请日:2015-02-10

    Inventor: HIDEKI TAKAKURA

    Abstract: An information processing device, comprising: a memory; and one or more central processing units coupled to the memory and configured to: control accesses to a device based on requests from users, record a start time of each access to the device and an end time of the access to the device, determine a load state of the device based on an elapsed time period from the start time to the end time, and limit, based on the load state of the device, a number of threads for one of the users, the threads being concurrently executed to access the device based on access requests to the device from the one of the users.

    Abstract translation: 一种信息处理装置,包括:存储器; 以及一个或多个中央处理单元,其耦合到所述存储器并且被配置为:基于来自用户的请求来控制对设备的访问,记录对设备的每次访问的开始时间以及对设备的访问的结束时间,确定负载 基于从开始时间到结束时间的经过时间的设备的状态,并且基于设备的负载状态来限制用户中的一个的线程数,并行执行线程以访问设备 基于来自用户之一的对设备的访问请求。

    Systems and methods for dynamic priority control
    100.
    发明授权
    Systems and methods for dynamic priority control 有权
    用于动态优先级控制的系统和方法

    公开(公告)号:US09146690B2

    公开(公告)日:2015-09-29

    申请号:US13750053

    申请日:2013-01-25

    CPC classification number: G06F3/0659 G06F3/061 G06F3/0673 G06F13/1642

    Abstract: System and methods are provided for dynamically managing a first-in/first-out (FIFO) command queue of a system controller. One or more commands are received into the command queue, a command being associated with a priority parameter. A current command first in line to be executed in the command queue is determined, the current command being associated with a first priority parameter. A second command associated with a second priority parameter is determined, the second priority parameter being largest among priority parameters associated with the one or more commands. A final priority parameter for the current command is computed based at least in part on the second priority parameter.

    Abstract translation: 系统和方法被提供用于动态地管理系统控制器的先进先出(FIFO)命令队列。 一个或多个命令被接收到命令队列中,该命令与优先级参数相关联。 确定首先在命令队列中执行的当前命令,当前命令与第一优先级参数相关联。 确定与第二优先级参数相关联的第二命令,所述第二优先级参数在与所述一个或多个命令相关联的优先级参数中最大。 至少部分地基于第二优先级参数来计算当前命令的最终优先级参数。

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