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公开(公告)号:US20180268914A1
公开(公告)日:2018-09-20
申请号:US15543957
申请日:2017-02-16
Inventor: Jian Zhao , Mo Chen , Xiong Xiong
IPC: G11C19/18
CPC classification number: G11C19/18 , G09G3/20 , G09G3/3677 , G09G2300/0408 , G09G2310/0267 , G09G2310/0286 , G11C19/184 , G11C19/28
Abstract: The embodiments of the present disclosure provide a shift register, a gate driving circuit and a display apparatus. The shift register comprises an input unit, a first reset unit, a node control unit, a gate-shaping unit, a first output unit and a second output unit. The shift register is configured to change a potential of a scan signal outputted from a driving signal output terminal, so as to produce a scan signal having a gate-shaped waveform.
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公开(公告)号:US20180267765A1
公开(公告)日:2018-09-20
申请号:US15540030
申请日:2017-04-11
Inventor: Shu Wen , Yichien Wen , Mingjong Jou
IPC: G06F3/14 , H01L27/32 , G09G3/3225 , H01L51/10
CPC classification number: G06F3/1446 , G09G3/3225 , G09G2300/026 , G09G2300/0408 , G09G2310/0264 , H01L27/3244 , H01L27/3276 , H01L27/3288 , H01L27/3293 , H01L51/0048 , H01L51/102
Abstract: The present invention provides a jointed display screen, which includes a plurality of OLED display screens (1) that are jointed to each other. Each of the OLED display screens (1) includes a flexible base plate (11) and an OLED panel (13) mounted on the flexible base plate (11). The OLED display screens (1) each include an effective display zone (AA) and a non-display zone (DD) located on an outer circumference of the effective display zone (AA). At a joint site between two adjacent ones of the OLED display screens (1), the non-display zones (DD) of the two adjacent OLED display screens (1) are both bent toward a back of the flexible base plate (11) so as to allow the effective display zones (AA) of the two adjacent OLED display screens (1) to joint to each other in a seamless manner to eliminate thereby eliminating a black strip or a black line occurring at the joint site, making an image displayed continuous, and improving an effect of viewing of the jointed display screen.
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公开(公告)号:US20180240409A1
公开(公告)日:2018-08-23
申请号:US15901712
申请日:2018-02-21
Applicant: SCT TECHNOLOGY, LTD.
Inventor: Eric LI , Juinn-Yan CHEN , Yi ZHANG , Heng LIU
IPC: G09G3/3283
CPC classification number: G09G3/3283 , G06F3/1446 , G09G3/3208 , G09G5/006 , G09G2300/026 , G09G2300/0408 , G09G2300/0804 , G09G2310/0291 , G09G2320/0242 , G09G2320/0285 , G09G2320/0673 , G09G2320/0693 , G09G2330/021 , G09G2330/026 , G09G2370/14
Abstract: An LED display device contains an LED display having an array of LED pixels and an electrical system. The electrical system includes a transmitter, a plurality of receiver chips each having a receiver circuitry, and a plurality of driver chips each having a driver circuitry. Alternatively, the receiver circuitry and the driver circuitry are integrated on one chip so that the electrical system contains a number of such chips. The transmitter comprises a memory storing a Gamma correction lookup table and a buffer for storing a LED calibration data. The transmitter receives data packets from a data source, performs Gamma encoding and LED calibration to the data packets. The receiver circuitry is coupled to the transmitter and receives data packets from the transmitter and sends PWM data to a group of LED drivers, which provides current sources to drive the LED array.
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公开(公告)号:US20180240395A1
公开(公告)日:2018-08-23
申请号:US15717419
申请日:2017-09-27
Inventor: Liqing LIAO , Hongmin LI , Ping SONG
IPC: G09G3/20
CPC classification number: G09G3/2092 , G09G3/20 , G09G3/3677 , G09G2300/0408 , G09G2300/043 , G09G2310/0267 , G09G2310/0286 , G09G2310/0289 , G09G2310/08 , G09G2330/023 , G11C19/28
Abstract: The present disclosure provides a gate driving circuit, a gate driving method and a display method. The gate driving circuit includes a pull-up node control circuitry, a pull-down node control circuitry, a display storage circuitry, a compensation storage circuitry and a compensation storage control circuitry. The compensation storage control circuitry is connected to an input terminal, a pull-down control voltage terminal, a pull-up node, a pull-down node, and a second terminal of the compensation storage circuitry, and configured to enable the pull-down control voltage terminal to be electrically connected to the second terminal of the compensation storage circuitry under the control of the input terminal so as to charge the compensation storage circuitry, and enable the second terminal of the compensation storage circuitry to be electrically connected to the pull-up node.
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公开(公告)号:US10043477B2
公开(公告)日:2018-08-07
申请号:US15128106
申请日:2016-08-31
Inventor: Yafeng Li
IPC: G09G3/36
CPC classification number: G09G3/3696 , G09G3/3648 , G09G3/3677 , G09G3/3688 , G09G2230/00 , G09G2300/0408 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/28
Abstract: The invention provides a GOA circuit, using the ninth and tenth TFTs and the resistor to control the voltage level of the third node, wherein ninth TFT having the gate connected to the m-th clock signal, the source connected to the first constant voltage, and the drain connected to one end of the resistor; the tenth TFT having the gate connected to the (m+2)-th clock signal, the source connected to the second constant voltage, and the drain connected to the other end of the resistor. Through the m-th and the (m+2)-th clock signal to control the ninth and the tenth TFTs to become conductive alternately, the present invention can charge and discharge the third node regularly to prevent the threshold voltage shift of the key TFT because the third node stays high for extended time, and ensure the stability of GOA circuit.
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公开(公告)号:US20180218665A1
公开(公告)日:2018-08-02
申请号:US15884570
申请日:2018-01-31
Applicant: Japan Display Inc.
Inventor: Ryutaro NITOBE
IPC: G09G3/20 , G09G3/36 , G06F3/044 , G06F3/041 , G02F1/1333
CPC classification number: G09G3/2092 , G02F1/13338 , G06F3/0412 , G06F3/0416 , G06F3/044 , G09G3/3607 , G09G3/3666 , G09G3/3677 , G09G3/3688 , G09G2300/0408 , G09G2300/0452 , G09G2310/06 , G09G2330/06 , G09G2370/08
Abstract: A display apparatus includes: a plurality of pixels arranged in a row-column configuration and divided into a plurality of units each including a plurality of rows; a plurality of scanning signal lines configured to select one row from the pixels; a plurality of pixel signal lines configured to supply pixel signals to the one row; a control circuit configured to output an image signal in which the pixel signals are time-division multiplexed and a plurality of separation control signals for separating the pixel signals from the image signal; and a separation circuit including signal lines and configured to separate the pixel signals from the image signal and output the pixel signals to the pixel signal lines based on the separation control signals. The control circuit switches ends to be supplied with the separation control signals between first ends and second ends of the signal lines in each unit.
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97.
公开(公告)号:US20180211614A1
公开(公告)日:2018-07-26
申请号:US15327640
申请日:2017-01-16
Inventor: Longqiang SHI , SHU-JHIH CHEN
CPC classification number: G09G3/36 , G02F1/13306 , G09G3/3677 , G09G2300/0408 , G09G2310/0264 , G09G2310/0286
Abstract: The present application discloses a pull down maintaining circuit, comprising: a first switch transistor, an input terminal is connected to a first direct current power source, and an output terminal outputting a scanning signal of the Nth level scanning line; a second switch transistor, an input terminal is connected to the first direct current power source, and an output terminal outputting a scanning electric level signal of the Nth level scanning line; a control unit for controlling the first and the second switch transistors to turn off in accordance with a low voltage outputted from the first and the second direct current power source, and the third direct current power source, and to control the first and the second switch transistors to normally turn on in accordance with a high voltage is outputted from the first and the second direct current power source, and the third direct current power source.
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公开(公告)号:US20180211609A1
公开(公告)日:2018-07-26
申请号:US15503705
申请日:2016-12-27
Inventor: Gang Wang , Lixuan Chen
IPC: G09G3/34 , G02F1/1362 , G02F1/1333 , G09G3/36
CPC classification number: G02F1/133305 , G02F1/1345 , G02F1/13452 , G02F1/13454 , G02F1/136227 , G02F1/136286 , G02F2201/42 , G09G3/3648 , G09G2300/0408 , G09G2300/0426
Abstract: The invention provides a display device, which employs ultra-thin flexible substrate with WOA disposed on both sides of the flexible substrate, wherein the WOA on the front side is directly connected to the active area, and the WOA on the back side passes through the holes in the flexible substrate to extend to the front side to connect to the active area. As such, the circuit area utilization is improved so that the same size of substrate area can carry almost twice the circuit structure to reduce the border width of the non-active area to achieve borderless or ultra-narrow borders.
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99.
公开(公告)号:US20180211606A1
公开(公告)日:2018-07-26
申请号:US15742723
申请日:2017-05-26
Inventor: Xiaoxiang ZHANG , Zheng LIU , Huibin GUO , Mingxuan LIU
IPC: G09G3/34
CPC classification number: G09G3/34 , G09G3/36 , G09G3/3677 , G09G2300/0408 , G09G2310/0286
Abstract: A shift register circuit and a driving method therefor, a gate line driving circuit and an array substrate, the shift register circuit includes: a charging sub-circuit for charging a pull-up node under the control of a signal input by an input signal terminal; an output sub-circuit for outputting, through an output terminal, a clock signal provided by a first clock signal terminal to serve as a drive signal, under control of an electric level of the pull-up node; a first pull-down sub-circuit for pulling down the pull-up node and the output terminal under the control of an electric level of a first pull-down node; and a reset sub-circuit for resetting the pull-up node and the output terminal under the control of a reset signal input by a reset signal terminal.
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公开(公告)号:US20180210254A1
公开(公告)日:2018-07-26
申请号:US15307007
申请日:2016-05-10
Inventor: Xiaoxiao WANG
IPC: G02F1/133 , G02F1/1362 , G09G3/36
CPC classification number: G02F1/13306 , G02F1/136286 , G09G3/36 , G09G3/3614 , G09G3/3648 , G09G3/3677 , G09G2300/0408 , G09G2310/0264
Abstract: A liquid crystal display circuit and a method for driving a liquid crystal display circuit are disclosed. The method has steps of: in a first driving period, a GOA driving circuit successively inputs driving signals to pixel units having positive polarities in each row, so that positive-polarity signals are written into the pixel units having the positive polarities by data lines; and in a second driving period, the GOA driving circuit successively inputs the driving signals to the pixel units having negative polarities in each row, so that negative-polarity signals are written into the pixel units having the negative polarities by the data lines.
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