公开(公告)号：US06369626B1

公开(公告)日：2002-04-09

申请号：US08966721

申请日：1997-11-10

申请人： Kevin S. Donnelly ,  Andy Chan ,  Thomas H. Lee ,  Wayne Richardson ,  Jared L. Zerbe ,  Chaofeng Huang ,  Clemenz L. Portmann ,  Grace Tsang

发明人： Kevin S. Donnelly ,  Andy Chan ,  Thomas H. Lee ,  Wayne Richardson ,  Jared L. Zerbe ,  Chaofeng Huang ,  Clemenz L. Portmann ,  Grace Tsang

IPC分类号： H03L300

CPC分类号： H03K5/1565 ,  H03L7/0896 ,  H03L7/093

摘要： A low pass filter having a first mode of operation and a second mode of operation. The low pass filter includes a charging circuit, a capacitor circuit, and low power circuitry coupled to the capacitor circuit and the charging circuit. The capacitor circuit stores a first differential voltage when the low pass filter is operating in the first mode of operation. The capacitor circuit stores a second differential voltage when the low pass filter is operating in the second mode of operation. The second differential voltage is substantially equal to the first differential voltage. The charging circuit may include a charging current source coupled to a current steering circuit. The low pass filter may further include a load circuit coupled to the current steering circuit and the low power circuitry. The low pass filter may be used in a delay locked loop circuit or a phase locked loop circuit.

摘要翻译： 具有第一操作模式和第二操作模式的低通滤波器。 低通滤波器包括充电电路，电容器电路和耦合到电容器电路和充电电路的低功率电路。 当低通滤波器在第一操作模式下操作时，电容器电路存储第一差分电压。 当低通滤波器在第二操作模式下工作时，电容器电路存储第二差分电压。 第二差分电压基本上等于第一差分电压。 充电电路可以包括耦合到电流转向电路的充电电流源。 低通滤波器还可以包括耦合到电流转向电路和低功率电路的负载电路。 低通滤波器可用于延迟锁定环电路或锁相环电路中。

公开(公告)号：US20020037065A1

公开(公告)日：2002-03-28

申请号：US09876586

申请日：2001-06-07

申请人： NEC Corporation

发明人： Satoshi Nakamura

IPC分类号： H03D003/24

CPC分类号： H03L7/14 ,  H03L7/087 ,  H03L7/0896 ,  H03L7/095 ,  H04L7/033

摘要： A clock signal reproduction device is provided which comprises: a VCO 7 for generating a clock signal; a phase comparator 1 for comparing the phases of an input data signal and the clock signal and generating a first control signal; a phase/frequency comparator 2 for comparing the phases of a signal divided from the clock signal and a reference clock signal and generating a second control signal; a mode switching selector 5 for selecting the first control signal and the second control signal; an analog frequency synchronization-IN detecting circuit 9 for detecting whether a phase difference between the signal divided from the clock signal and the reference clock signal is within a predetermined range; and a digital frequency synchronization-OUT detecting circuit 11 for detecting whether a phase difference between the signal divided from the clock signal and the reference clock signal is outside of the predetermined range.

摘要翻译： 提供了一种时钟信号再现装置，包括：用于产生时钟信号的VCO7; 相位比较器1，用于比较输入数据信号和时钟信号的相位并产生第一控制信号; 相位/频率比较器2，用于比较从时钟信号和参考时钟信号分离的信号的相位，并产生第二控制信号; 用于选择第一控制信号和第二控制信号的模式切换选择器5; 用于检测从时钟信号和参考时钟信号分离的信号之间的相位差是否在预定范围内的模拟频率同步IN检测电路9; 以及数字频率同步输出检测电路11，用于检测从时钟信号和参考时钟信号分离的信号之间的相位差是否在预定范围之外。

公开(公告)号：US06326852B1

公开(公告)日：2001-12-04

申请号：US09649197

申请日：2000-08-28

申请人： Myles H. Wakayama

发明人： Myles H. Wakayama

IPC分类号： H03L7093

CPC分类号： H03L7/0898 ,  H03L7/0896

摘要： A high precision charge pump used in a phase-lock-loop incorporating a phase/frequency detector is designed and constructed to substantially eliminate the effects of DC offset and glitch errors on the charge pump output current. The high precision charge pump is constructed of parallel current paths each having a central node which is, in turn, connected to a feedback element. The feedback element defines a feedback current which is applied to the charge pump so as to maintain the two central nodes at an equi-potential level and to maintain the value of the pump-down current exactly equal to the value of the pump-up current output by the device.

公开(公告)号：US06316977B1

公开(公告)日：2001-11-13

申请号：US09617201

申请日：2000-07-14

申请人： Winslow Sargeant

发明人： Winslow Sargeant

IPC分类号： H03L706

CPC分类号： H03L7/0896

摘要： There is provided a low charge-injection charge pump for supplying charge into a charge summing node to generate a low noise output voltage. The charge pump includes a PMOS current source coupled between a first PMOS switch and a charge summing node. The charge pump also has a NMOS current source coupled between a first NMOS switch and the charge summing node. The switches operate to turn ON the current sources to allow charge to flow into, or out of, the charge summing node to increase or decrease the voltage present on the charge summing node. The positioning of the switches away from the charge summing node serves to prevent channel charges in the first PMOS switch and in the first NMOS switch from flowing into the charge summing node when either of the two switches are turned OFF. Furthermore, a second PMOS switch and a second NMOS switch are employed to dissipate channel charges flowing from the channels of the first PMOS and NMOS switches when those switches are turned OFF. The second PMOS and NMOS switches also operate to bias the PMOS and NMOS current sources so that they do not conduct when the first PMOS and NMOS switches are turned OFF. The dissipation of channel charge and the biasing of the current sources operate to reduce noise on the charge summing node.

摘要翻译： 提供了一种低电荷注入电荷泵，用于向电荷求和节点提供电荷以产生低噪声输出电压。 电荷泵包括耦合在第一PMOS开关和电荷求和节点之间的PMOS电流源。 电荷泵还具有耦合在第一NMOS开关和电荷求和节点之间的NMOS电流源。 开关操作以接通电流源以允许电荷流入或流出电荷求和节点以增加或减少电荷求和节点上存在的电压。 远离充电求和节点的开关的定位用于当两个开关中的任一个关闭时，阻止第一PMOS开关中和第一NMOS开关中的沟道电荷流入电荷求和节点。 此外，当这些开关断开时，采用第二PMOS开关和第二NMOS开关来耗散从第一PMOS和NMOS开关的沟道流动的沟道电荷。 第二个PMOS和NMOS开关也工作以使PMOS和NMOS电流源偏置，使得它们在第一个PMOS和NMOS开关截止时不导通。 通道电荷的消耗和电流源的偏置操作以减少电荷求和节点上的噪声。

公开(公告)号：US06212248B1

公开(公告)日：2001-04-03

申请号：US09040688

申请日：1998-03-18

申请人： Masayuki Hayashi ,  Robert J. Savaglio

发明人： Masayuki Hayashi ,  Robert J. Savaglio

IPC分类号： H03D302

CPC分类号： H03L7/0893 ,  H03L7/0891 ,  H03L7/0896 ,  H04L7/033

摘要： A shared path phase detector and phase indicator circuit provide a phase locked loop circuit for which loading and wiring dependencies are greatly reduced. The phase detector circuit is provided for receiving a reference clock and a second clock. The phase detector circuit provides a separate and unique signal for indicating the magnitude of the difference between the phase of the reference clock and the second clock, regardless of whether the second clock is leading or lagging the first clock. The phase indicator circuit detects whether the second clock is leading or lagging the first clock, and routes the pulses on a first internal signal path to generate either increment or decrement pulses depending on whether the second clock is lagging or leading, respectively. The generation of the increment and decrement pulses is also routed on the first internal signal path, which provides a phase locked loop circuit that does not require matched loading and custom wiring on the internal increment and the decrement paths as required in the prior art.

摘要翻译： 共享路径相位检测器和相位指示器电路提供了大大减少负载和布线依赖性的锁相环电路。 相位检测器电路用于接收参考时钟和第二时钟。 相位检测器电路提供单独且独特的信号，用于指示参考时钟的相位与第二时钟之间的差的大小，而不管第二时钟是引导还是滞后于第一时钟。 相位指示器电路检测第二时钟是否在前进或滞后于第一时钟，并且将脉冲路由在第一内部信号路径上以分别根据第二时钟是滞后还是前导而产生增量或递减脉冲。 增量和递减脉冲的产生也在第一内部信号路径上路由，其提供了锁相环电路，其不需要现有技术中所需的内部增量和递减路径上的匹配加载和定制接线。

公开(公告)号：US06198355B1

公开(公告)日：2001-03-06

申请号：US09266844

申请日：1999-03-12

申请人： Björn Lindquist ,  Magnus Nilsson

发明人： Björn Lindquist ,  Magnus Nilsson

IPC分类号： H03L7085

CPC分类号： H03L7/0891 ,  H03D13/004 ,  H03L7/0896 ,  H03L7/0898 ,  H03L7/1976

摘要： There is disclosed a phase detector which triggers on both rising and falling edges of an input pulse signal. This effectively doubles the frequency of the input signal. When the phase detector is used in a phase locked loop, the doubled frequency means that a lower division ratio can be used, thereby reducing any noise contribution introduced thereby.

摘要翻译： 公开了一种在输入脉冲信号的上升沿和下降沿触发的相位检测器。 这有效地使输入信号的频率加倍。 当相位检测器用于锁相环时，双倍频率意味着可以使用较低的分频比，从而减少由此引入的任何噪声贡献。

公开(公告)号：US06184732B2

公开(公告)日：2001-02-06

申请号：US09370622

申请日：1999-08-06

申请人： Luke A. Johnson ,  Timothy E. Fiscus

发明人： Luke A. Johnson ,  Timothy E. Fiscus

IPC分类号： H03L706

CPC分类号： H03L7/0896

摘要： An embodiment of the invention is directed to a circuit including first and second filter nodes for being connected to a filter and first and second bypass nodes corresponding to the first and second filter nodes, respectively. A charge transfer circuit having at least one charge transfer node is to be alternatively coupled to one of the filter nodes and a corresponding one of the bypass nodes for transferring charge to control a differential voltage of the filter nodes. First and second amplifiers are to buffer the voltages on the first and second filter nodes at first and second outputs which are coupled to the first and second bypass nodes, respectively. The output voltage of each amplifier can be adjusted according to a difference between a control voltage and a common mode voltage of the first and second nodes.

公开(公告)号：US06104251A

公开(公告)日：2000-08-15

申请号：US143945

申请日：1998-08-31

申请人： Delvan A. Ramey ,  Vincent von Kaenel

发明人： Delvan A. Ramey ,  Vincent von Kaenel

IPC分类号： G06F1/08 ,  H03L7/089 ,  H03L7/14 ,  H03L7/199 ,  H03L7/085 ,  H03L7/18

CPC分类号： H03L7/199 ,  G06F1/08 ,  H03L7/0893 ,  H03L7/0896 ,  H03L7/14

摘要： The present invention is directed to apparatus and methods for reducing transient signals in phase locked loop (PLL) circuits of central processing units. One aspect of the present invention is directed to a method and apparatus that disables a charge pump circuit in a phase locked loop circuit when a frequency change in the output signal of the PLL circuit is implemented to limit transient signals generated by the PLL. Another aspect of the present invention is directed to a method and apparatus for coordinating a change in divider values for frequency dividers in a PLL of a CPU to limit transient signals from the PLL.

摘要翻译： 本发明涉及用于减少中央处理单元的锁相环（PLL）电路中的瞬态信号的装置和方法。 本发明的一个方面涉及一种方法和装置，当PLL电路的输出信号的频率变化被实现以限制PLL产生的瞬态信号时，禁用锁相环电路中的电荷泵电路。 本发明的另一方面涉及一种用于协调CPU的PLL中的分频器的分频值的变化以限制来自PLL的瞬态信号的方法和装置。

公开(公告)号：US6067336A

公开(公告)日：2000-05-23

申请号：US164842

申请日：1998-10-01

申请人： Yung-Chow Peng

发明人： Yung-Chow Peng

IPC分类号： H03L7/08 ,  H03L7/081 ,  H03L7/089 ,  H03L7/16 ,  H03D3/24

CPC分类号： H03L7/0896 ,  H03L7/0812 ,  H03L7/16 ,  H03L2207/14 ,  H03L7/0802

摘要： A charge pump includes a constant current source, a charging field effect transistor (FET) and a discharging FET coupled to mirror a current in the constant current source, a first pair of switching transistors controlling a charging current flow between a charging path and a first standby path, a second pair of switching transistors controlling a discharging current flow between a discharging path and a second standby path, a first and a second pairs of transistors isolating output and input of the charge pump and keeping unchanged the drain voltages of the charging and the discharging FETs. The two pairs of switching transistors in conjunction with the two pairs of transistors act to keep the charging and the discharging currents always on. Accordingly, the switching performance of the disclosed charge pump is much better than prior arts without using current-steering amplifier and is capable of high frequency operation. In addition, charge feedthrough, jitters, and unbalanced output waveform is not going to be significant in the invention. Consequently, the invention provides a device-saving charge pump supplying matched up and down current pulse without charge feedthrough.

摘要翻译： 电荷泵包括恒流源，充电场效应晶体管（FET）和耦合以反射恒流源中的电流的放电FET;第一对开关晶体管，控制充电路径和第一 控制放电路径和第二备用路径之间的放电电流的第二对开关晶体管，隔离电荷泵的输出和输入的第一和第二对晶体管，并保持充电的漏极电压和 放电FET。 结合两对晶体管的两对开关晶体管用于保持充电和放电电流始终导通。 因此，所公开的电荷泵的开关性能比现有技术好得多，而不使用电流导向放大器，并且能够进行高频操作。 此外，在本发明中，充电馈通，抖动和不平衡输出波形并不显着。 因此，本发明提供了一种节省设备的电荷泵，其提供匹配的上下电流脉冲，而无需充电馈通。

公开(公告)号：US5847614A

公开(公告)日：1998-12-08

申请号：US751224

申请日：1996-11-15

申请人： Barrie Gilbert ,  Daryl Carbonari ,  Eberhard Brunner ,  Fred Weiss

发明人： Barrie Gilbert ,  Daryl Carbonari ,  Eberhard Brunner ,  Fred Weiss

IPC分类号： H03L7/08 ,  H03L7/089 ,  H03L7/14 ,  H03L7/18 ,  H03L7/093

CPC分类号： H03L7/18 ,  H03L7/0891 ,  H03L7/0896 ,  H03L7/14 ,  H03L7/0802

摘要： A charge pump in a phase locked loop is enabled only when a loop filter needs to be updated, thereby reducing the power consumption of the charge pump. The charge pump is enabled or disabled in response to an enable signal which is generated by a latch. The enable signal is activated by look-ahead signals which are activated in advance of either a pulse from a reference signal or a pulse from a variable signal so as to allow the charge pump to stabilize before providing the charge current to update the loop filter. Logic signals from a programmable divider and reference signal generator are used to generate the look-ahead signals. The charge pump is disabled by a reset signal from a phase-frequency detector after the loop filter is updated. The charge pump includes a current switch for generating source and sink charge currents in response to pump-up and pump-down control signals. A bias cell provides two reference signals to the current switch. The reference signals are disabled in response to an enable signal, thereby disabling the current switch and reducing the power consumption of the charge pump.

摘要翻译： 只有在需要更新环路滤波器时才能启用锁相环中的电荷泵，从而降低电荷泵的功耗。 响应于由锁存器产生的使能信号，电荷泵被使能或禁止。 使能信号由先前信号激活，该信号在来自参考信号的脉冲或来自可变信号的脉冲之前被激活，以便在提供充电电流以更新环路滤波器之前允许电荷泵稳定。 来自可编程分频器和参考信号发生器的逻辑信号用于产生先行信号。 在更新环路滤波器之后，电荷泵由相位频率检测器的复位信号禁止。 电荷泵包括电流开关，用于响应于泵浦和抽吸控制信号产生源极和吸收器充电电流。 偏置单元为电流开关提供两个参考信号。 参考信号响应于使能信号被禁用，从而禁用电流开关并降低电荷泵的功率消耗。