公开(公告)号：US20120177635A1

公开(公告)日：2012-07-12

申请号：US13281209

申请日：2011-10-25

Applicant: LAWREN WU ,  MERCEDESZ BALAZS ,  HANS BRIGHTBILL ,  ANDY CHAN ,  YVONNE CHEN ,  ANAN CHUNTHARAPAL ,  MARK DENNIS ,  TERENCE WONG

Inventor： LAWREN WU ,  MERCEDESZ BALAZS ,  HANS BRIGHTBILL ,  ANDY CHAN ,  YVONNE CHEN ,  ANAN CHUNTHARAPAL ,  MARK DENNIS ,  TERENCE WONG

IPC: A61K39/395

CPC classification number: C07K16/4291 ,  A01K67/0278 ,  A01K2217/072 ,  A01K2227/105 ,  A01K2267/0387 ,  A61K2039/505 ,  C07K2317/21 ,  C07K2317/24 ,  C07K2317/41 ,  C07K2317/73

Abstract: The present application relates to apoptotic anti-IgE antibodies, nucleic acid encoding the same, therapeutic compositions thereof, and their use in the treatment of IgE-mediated disorders.

Abstract translation: 本申请涉及凋亡性抗IgE抗体，编码它的核酸，其治疗组合物及其在治疗IgE介导的病症中的用途。

公开(公告)号：US08200961B2

公开(公告)日：2012-06-12

申请号：US11679108

申请日：2007-02-26

Applicant: Pramila Srinivasan ,  John Princen ,  Andy Chan ,  Paul Mielke ,  Rob Wheeler

Inventor： Pramila Srinivasan ,  John Princen ,  Andy Chan ,  Paul Mielke ,  Rob Wheeler

IPC: H04L29/08

CPC classification number: G06F21/79

Abstract: A technique for securing a flash memory block in a secure device system involves cryptographic techniques including the generation of a Message Authentication Code (MAC). The MAC may be generated each time a file is saved to one or more data blocks of a flash memory device and stored with the file's metadata and to each of the data blocks. A technique for reading and storing versioned files may be employed when applications utilize versioning.

Abstract translation: 用于将闪存块保护在安全设备系统中的技术涉及包括生成消息认证码（MAC）的密码技术。 每当将文件保存到闪存设备的一个或多个数据块并且与文件的元数据一起存储并存储到每个数据块时，可以生成MAC。 当应用程序利用版本控制时，可以采用读取和存储版本化文件的技术。

公开(公告)号：USD618141S1

公开(公告)日：2010-06-22

申请号：US29340891

申请日：2009-07-28

Applicant: Andy Chan

Designer： Andy Chan

公开(公告)号：US06397345B1

公开(公告)日：2002-05-28

申请号：US09169361

申请日：1998-10-09

Applicant: Paul Edmonds ,  Yi Zhang ,  Chang Xu ,  Priyen Doshi ,  Stephen Co ,  Michael P. Tel ,  Andy Chan

Inventor： Paul Edmonds ,  Yi Zhang ,  Chang Xu ,  Priyen Doshi ,  Stephen Co ,  Michael P. Tel ,  Andy Chan

IPC: H02H305

CPC classification number: G06F11/2007 ,  G06F11/2005 ,  G06F11/2053 ,  G06F2201/85 ,  H04B1/74

Abstract: A computer system includes a plurality of interdependent processors. Each interdependent processor executes an independent operating system image without sharing file system state information, and each interdependent processor further has a network access card with a first network connection and a second network connection. The computer system has a first active backplane coupled to each first network connection of each processor; a second active backplane coupled to each second network connection of each processor, the second active backplane operating in lieu of the first active backplane in case of a fail-over; and one or more peripherals connected to each of the first and second active backplanes and responsive to data requests transmitted over the first and second active backplanes.

Abstract translation: 计算机系统包括多个相互依赖的处理器。 每个相互依赖的处理器在不共享文件系统状态信息的情况下执行独立的操作系统映像，并且每个相互依赖的处理器还具有具有第一网络连接和第二网络连接的网络访问卡。 计算机系统具有耦合到每个处理器的每个第一网络连接的第一有源底板; 耦合到每个处理器的每个第二网络连接的第二有源背板，在故障转移的情况下第二主动背板代替第一有源背板操作; 以及连接到第一和第二活动背板中的每一个的一个或多个外围设备，并响应于在第一和第二活动背板上传输的数据请求。

公开(公告)号：US06393599B1

公开(公告)日：2002-05-21

申请号：US09347873

申请日：1999-07-06

Applicant: Andy Chan

Inventor： Andy Chan

IPC: G06F1108

CPC classification number: H04L27/233

Abstract: A multi-chip data decoder implemented for symmetric differential phase shift keying (SDPSK) or symmetric differential quadriphase shift keying (SDQPSK) modulation formats which uses multiple-chip observation intervals to improve performance over conventional symbol-to-symbol differential detection. Input phases &phgr;k, &phgr;k−1, &phgr;k−2, and &phgr;k−3 are detected by comparing a received vector of data bits and parity bits, which contains phase transition information over multiple chips, to the set of ideal vectors of data bits and parity bits, which contain all phase transition possibilities over that set of chips in a noiseless environment. The multi-chip data detector for decoding incoming modulated data comprises a phase-difference encoder (10, 100) arranged to encode phase-differences &phgr;k−2-&phgr;k−3, &phgr;k−1-&phgr;k−2, &phgr;k-&phgr;k−1, &phgr;k-&phgr;k−2, &phgr;k−1-&phgr;k−3, and &phgr;k-&phgr;k−3 of the incoming modulated data during a multiple-chip observation interval to produce a received vector of a predetermined number of data bits and parity bits; a decoder (20, 200) arranged to decode the received vector to produce multiple bit decisions by mapping the received vector with a set of ideal vectors; and a majority voter (30, 300) arranged to choose a bit estimate from the multiple bit decisions by way of a majority rule to produce a final detected symbol from the incoming modulated data during the multiple-chip observation interval. The multi-chip data detection technique performs multiple-chip comparisons in an efficient manner, providing a significant performance and implementation improvement over conventional symbol-to-symbol differential detection while realizing design gate savings of up to 90%.

Abstract translation: 实现用于对称差分相移键控（SDPSK）或对称差分四相移键控（SDQPSK）调制格式的多芯片数据解码器，其使用多码片观察间隔来提高性能，超越常规符号到符号差分检测。 通过将包含多个码片上的相变信息的数据比特和奇偶校验位的接收矢量与数据比特和奇偶校验的理想向量的集合进行比较来检测phik，phik-1，phik-2和phik-3的输入相位 位，其在无噪声环境中包含该组芯片上的所有相变可能性。 用于对输入的调制数据进行解码的多芯片数据检测器包括一个相位差编码器（10,100），被布置成编码相差phik-2-phik-3，phik-1-phik-2，phik-phik-1， phik-phik-2，phik-1-phik-3和phik-phik-3在多芯片观察间隔期间输入调制数据，以产生预定数量的数据位和奇偶校验位的接收向量; 解码器（20,200），被布置为通过用一组理想向量映射所述接收的矢量来解码所述接收的矢量以产生多个比特决定; 以及多数选民（30,300），其被布置为通过多数规则从多位决策中选择比特估计，以在多码片观察间隔期间从输入的调制数据产生最终检测符号。 多芯片数据检测技术以有效的方式进行多芯片比较，提供了比传统符号到符号差分检测的显着性能和实现改进，同时实现高达90％的设计门节省。

公开(公告)号：US06369626B1

公开(公告)日：2002-04-09

申请号：US08966721

申请日：1997-11-10

Applicant: Kevin S. Donnelly ,  Andy Chan ,  Thomas H. Lee ,  Wayne Richardson ,  Jared L. Zerbe ,  Chaofeng Huang ,  Clemenz L. Portmann ,  Grace Tsang

Inventor： Kevin S. Donnelly ,  Andy Chan ,  Thomas H. Lee ,  Wayne Richardson ,  Jared L. Zerbe ,  Chaofeng Huang ,  Clemenz L. Portmann ,  Grace Tsang

IPC: H03L300

CPC classification number: H03K5/1565 ,  H03L7/0896 ,  H03L7/093

Abstract: A low pass filter having a first mode of operation and a second mode of operation. The low pass filter includes a charging circuit, a capacitor circuit, and low power circuitry coupled to the capacitor circuit and the charging circuit. The capacitor circuit stores a first differential voltage when the low pass filter is operating in the first mode of operation. The capacitor circuit stores a second differential voltage when the low pass filter is operating in the second mode of operation. The second differential voltage is substantially equal to the first differential voltage. The charging circuit may include a charging current source coupled to a current steering circuit. The low pass filter may further include a load circuit coupled to the current steering circuit and the low power circuitry. The low pass filter may be used in a delay locked loop circuit or a phase locked loop circuit.

Abstract translation: 具有第一操作模式和第二操作模式的低通滤波器。 低通滤波器包括充电电路，电容器电路和耦合到电容器电路和充电电路的低功率电路。 当低通滤波器在第一操作模式下操作时，电容器电路存储第一差分电压。 当低通滤波器在第二操作模式下工作时，电容器电路存储第二差分电压。 第二差分电压基本上等于第一差分电压。 充电电路可以包括耦合到电流转向电路的充电电流源。 低通滤波器还可以包括耦合到电流转向电路和低功率电路的负载电路。 低通滤波器可用于延迟锁定环电路或锁相环电路中。

公开(公告)号：US06230190B1

公开(公告)日：2001-05-08

申请号：US09169360

申请日：1998-10-09

Applicant: Paul Edmonds ,  Yi Zhang ,  Chang Xu ,  Priyen Doshi ,  Stephen Co ,  Michael P. Tel ,  Andy Chan

Inventor： Paul Edmonds ,  Yi Zhang ,  Chang Xu ,  Priyen Doshi ,  Stephen Co ,  Michael P. Tel ,  Andy Chan

IPC: G06F15167

CPC classification number: H04L67/1034 ,  H04L29/06 ,  H04L67/00 ,  H04L67/10 ,  H04L67/1002 ,  H04L69/329 ,  H04L2029/06054

Abstract: A computer system has a plurality of processors, each processor executing an independent operating system image without sharing file system state information. The system includes an active backplane coupled to the plurality of processors; and one or more data storage devices coupled to the active backplane for satisfying data requests from the plurality of processors, each of the data storage devices being adapted to secure a file when one processor writes to the file and to release the file when the processor completes operation on the file.

Abstract translation: 计算机系统具有多个处理器，每个处理器执行独立的操作系统图像而不共享文件系统状态信息。 该系统包括耦合到多个处理器的有源底板; 以及耦合到所述活动背板的一个或多个数据存储设备，用于满足来自所述多个处理器的数据请求，所述数据存储设备中的每一个适于在一个处理器写入所述文件时保护文件，并且当所述处理器完成时释放所述文件 对文件进行操作

公开(公告)号：US08518237B2

公开(公告)日：2013-08-27

申请号：US13119990

申请日：2009-09-14

Applicant: Andy Chan ,  Lawrence Milesky

Inventor： Andy Chan ,  Lawrence Milesky

IPC: G01N27/26 ,  G01N27/404

CPC classification number: G01N27/404

Abstract: The service life of amperometric electrochemical oxygen sensors is increased by operating the electrodes of such sensors at a polarization voltage suitable for measuring the oxygen content of samples only during calibration or when measuring such samples and thereafter modulating the polarization voltage to a lower voltage such that substantially no electrical current is produced by the electrodes.

Abstract translation: 电流型电化学氧传感器的使用寿命通过以适于仅在校准期间或在测量这些样品时测量样品的氧含量的极化电压操作这些传感器的电极而增加，此后将极化电压调制到较低电压，使得基本上 电极不产生电流。

公开(公告)号：US20080117679A1

公开(公告)日：2008-05-22

申请号：US11679108

申请日：2007-02-26

Applicant: Pramila Srinivasan ,  John Princen ,  Andy Chan ,  Paul Mielke ,  Rob Wheeler

Inventor： Pramila Srinivasan ,  John Princen ,  Andy Chan ,  Paul Mielke ,  Rob Wheeler

IPC: G11C16/22

CPC classification number: G06F21/79

Abstract: A technique for securing a flash memory block in a secure device system involves cryptographic techniques including the generation of a Message Authentication Code (MAC). The MAC may be generated each time a file is saved to one or more data blocks of a flash memory device and stored with the file's metadata and to each of the data blocks. A technique for reading and storing versioned files may be employed when applications utilize versioning.

Abstract translation: 用于将闪存块保护在安全设备系统中的技术涉及包括生成消息认证码（MAC）的密码技术。 每当将文件保存到闪存设备的一个或多个数据块并且与文件的元数据一起存储并存储到每个数据块时，可以生成MAC。 当应用程序利用版本控制时，可以采用读取和存储版本化文件的技术。

公开(公告)号：US20060227927A1

公开(公告)日：2006-10-12

申请号：US11448259

申请日：2006-06-06

Applicant: Kueck Lee ,  Andy Chan

Inventor： Kueck Lee ,  Andy Chan

IPC: G06M1/00

CPC classification number: H03K17/167 ,  H03K19/00384

Abstract: An integrated circuit device having an output driver circuit and a control circuit. The output driver circuit outputs a first signal having a signal level according to a control value. The control circuit is coupled to receive the first signal from the output driver and adjusts the control value by a first increment until a transition event is detected. After the transition event is detected, the control circuit adjusts the control value by a second increment, the second increment being smaller than the first increment.

Abstract translation: 一种具有输出驱动电路和控制电路的集成电路装置。 输出驱动电路根据控制值输出具有信号电平的第一信号。 控制电路被耦合以从输出驱动器接收第一信号，并且通过第一增量调整控制值，直到检测到转换事件。 在检测到转换事件之后，控制电路将控制值调整第二增量，第二增量小于第一增量。