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276 条记录 (耗时 0.015 秒)

    Two-terminal transistor memory utilizing saturation operation
    91.
    发明授权
    Two-terminal transistor memory utilizing saturation operation 失效
    两端晶体管存储器利用饱和运行

    公开(公告)号：US3699542A

    公开(公告)日：1972-10-17

    申请号：US3699542D

    申请日：1970-12-31

    申请人： BELL TELEPHONE LABOR INC

    发明人： LYNES DENNIS JOSEPH ,  MAR JERRY

    IPC分类号： G11C11/39 ,  G11C11/40

    CPC分类号： G11C11/39

    摘要： A semiconductor memory cell containing a dual emitter transistor having an uncontacted base is operated as a two-terminal device. A voltage pulse circuit connected to the first emitter, a conduction detector voltage pulse circuit is connected to the second emitter, and a resistor is connected between the first emitter and the collector. Bit information is written into the cell by setting the potential of the base of two values, which represent respectively a ''''1'''' and ''''0.'''' A ''''1'''' is written into the cell by applying appropriate polarity and amplitude voltage pulses to the two emitters to bias the first emitter-base junction to avalanche breakdown and to forward bias the second emitter-base and collector-base junctions so as to cause the transistor to operate in saturation. To read out information previously stored in the cell and write a ''''0'''' into the cell, a positive going voltage pulse is applied by the voltage pulse circuit to the first emitter.

    摘要翻译： 包含具有未接触基极的双发射极晶体管的半导体存储单元作为双端器件工作。 连接到第一发射极的电压脉冲电路，导通检测器电压脉冲电路连接到第二发射极，电阻连接在第一发射极和集电极之间。 通过设置分别表示“1”和“0”的两个值的基数的电位，将位信息写入单元。 通过对两个发射极施加适当的极性和幅度电压脉冲来将“1”写入单元，以将第一发射极 - 基极结偏置成雪崩击穿，并且使第二发射极基极和集电极 - 基极结正向偏置，从而使 晶体管工作在饱和状态。 为了读取先前存储在单元中的信息并将“0”写入单元，正电压脉冲由电压脉冲电路施加到第一发射极。

    Two-terminal transistor memory utilizing collector-base avalanche breakdown
    92.
    发明授权
    Two-terminal transistor memory utilizing collector-base avalanche breakdown 失效
    使用收集器基座AVALANCHE断开的两端子晶体管存储器

    公开(公告)号：US3699540A

    公开(公告)日：1972-10-17

    申请号：US3699540D

    申请日：1970-12-31

    申请人： BELL TELEPHONE LABOR INC

    发明人： LYNES DENNIS JOSEPH ,  MAR JERRY

    IPC分类号： G11C11/39 ,  G11C11/40

    CPC分类号： G11C11/39

    摘要： A semiconductor memory cell containing a single transistor having an uncontacted base is operated as a two-terminal device with a voltage pulse circuit coupled to the collector and a conduction detector coupled to the emitter. Bit information is written into the cell by setting the potential of the base to one of two values, which represent respectively a ''''1'''' and a ''''0.'''' A ''''1'''' is written into the cell by applying a positive polarity voltage pulse to the collector of sufficient amplitude to bias the collector-base junction to avalanche breakdown and to forward-bias the emitter-base junction, thereby causing transistor conduction. To read out information previously stored in the cell and to write a ''''0'''' into the cell, a positive polarity voltage pulse is applied to the collector; the positive pulse is of insufficient amplitude to bias the collector-base junction to avalanche breakdown.

    摘要翻译： 包含具有未接触基极的单个晶体管的半导体存储单元作为具有耦合到集电极的电压脉冲电路和耦合到发射极的导电检测器的双端器件而工作。 通过将基数的电位设置为分别表示“1”和“0”的两个值之一，将位信息写入单元。 通过向集电极施加足够大的幅度的正极性电压脉冲来将“1”写入单元，以将集电极 - 基极结偏置成雪崩击穿并且使发射极 - 基极结正向偏置，从而导致晶体管导通。 为了读出先前存储在单元中的信息并将“0”写入单元，向集电极施加正极性电压脉冲; 正脉冲幅度不足以将集电极 - 基极结偏置成雪崩击穿。

    Voltage-stable negative resistance device
    93.
    发明授权
    Voltage-stable negative resistance device 失效
    电压稳定的负极电阻器件

    公开(公告)号：US3576572A

    公开(公告)日：1971-04-27

    申请号：US3576572D

    申请日：1968-07-15

    申请人： IBM

    发明人： BRASLAU NORMAN

    IPC分类号： G11C11/39 ,  H01L47/00 ,  H03K3/02 ,  G11C11/36 ,  H03K3/31

    CPC分类号： G11C11/39 ,  H01L47/00 ,  H03K3/02

    摘要： A voltage-stable, negative resistance device is provided that comprises a bulk material which is subjected to both a selected Radio Frequency electric field and a DC bias electric field. A pair of such devices provides a memory when mounted in a waveguide that is subjected to either a standing wave field or a traveling wave field.