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公开(公告)号：US20190289524A1
公开(公告)日：2019-09-19
申请号：US16429442
申请日：2019-06-03
摘要： A system having a first data processing unit and a second data processing unit, wherein the first data processing unit has a first communication interface and the second data processing unit has a second communication interface, and the first communication interface and the second communication interface are connected by means of a signal line, and a monitoring unit, which is set up and provided for the purpose of resetting the first data processing unit and/or the second data processing unit to a defined operational state by means of a reset signal. The monitoring unit is connected to the signal line and provided to monitor a signal, which signals a phase of data transmission between the first communication interface and the second communication interface using a predetermined voltage level of the signal.
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92.发明授权公开(公告)号：US10409698B2
公开(公告)日：2019-09-10
申请号：US13640282
申请日：2011-04-08
申请人： Martin Dresler , Johannes Hauf , Martin Schmitz
发明人： Martin Dresler , Johannes Hauf , Martin Schmitz
IPC分类号： G06F11/26 , G01R31/319
摘要： A method for performing a plurality of tests on a device under test comprises performing a plurality of tests on a device under test. Each test of the plurality of tests comprises a foreground process and a background process. The foreground process comprises a setup process during which a desired test mode is set. The background process comprises an upload process during which data captured from the device under test is provided. The foreground process is executed with a higher priority than the background process, thereby minimizing a delay between a start of consecutive tests of the device under test.
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公开(公告)号：US10402288B2
公开(公告)日：2019-09-03
申请号：US15782181
申请日：2017-10-12
发明人： Huang-Wen Su , Shi-Tsan Lin
IPC分类号： G06F11/00 , G06F11/22 , G06F11/263 , G06F13/42 , G06F11/273 , G06F11/26
摘要： A universal serial bus (USB) testing method includes selecting a selected test mode from test modes, creating a USB communication link between a USB device and a testing fixture board, generating, by the testing fixture board, a test-triggering instruction corresponding to the selected test mode according to the selected test mode, sending the test-triggering instruction to the USB device with the USB communication link, generating, by the USB device, a testing packet corresponding to the selected test mode according to the test-triggering instruction, and outputting the testing packet repeatedly from at least one external port of the USB device.
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公开(公告)号：US10384689B2
公开(公告)日：2019-08-20
申请号：US15617610
申请日：2017-06-08
申请人： Robert Bosch GmbH
发明人： Jaroslaw Topp , Dieter Thoss , Margit Mueller , Thomas Hartgen
摘要： A method for operating a control unit of a motor vehicle. A status inquiry is transmitted by a watchdog unit to a first monitoring unit, which is implemented on a first processor core of a multicore processor. A status response is ascertained by the first monitoring unit as a function of the status inquiry. A fault is ascertained by the watchdog unit as a function of the status response.
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公开(公告)号：US10372571B2
公开(公告)日：2019-08-06
申请号：US15117029
申请日：2015-02-11
发明人： Wensheng Cao , Yanqing Jing , Jun Li , Kang Du , Tianping Geng
摘要： The present disclosure discloses a method and an apparatus for testing the compatibility of a 3D engine. The method includes: acquiring a hardware capability parameter of a graphics card to be simulated, the hardware capability parameter recording a capability supported by the graphics card; running a predetermined 3D engine according to the hardware capability parameter; and determining, according to a result of running the 3D engine, whether the 3D engine is compatible with the graphics card to be simulated. The present disclosure solves the technical problem that a hardware testing environment needs to be repeatedly built to test the compatibility of the 3D engine on different graphics cards, thereby achieving technical effects of simulating different virtual graphics cards to implement testing in a hardware testing environment built once, and shortening a testing period.
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公开(公告)号：US10360992B2
公开(公告)日：2019-07-23
申请号：US15157799
申请日：2016-05-18
发明人： Dong-Gun Kim , Je-Young Park , Byung-Soo Moon
IPC分类号： G11C5/14 , G11C29/56 , G01R19/00 , G11C29/50 , G11C29/08 , G01R31/317 , G06F11/263 , G11C29/12 , G01R31/28 , G11C29/10 , G06F11/277 , G01R31/319 , G06F11/26 , G01R17/00
摘要： A test device includes a data driver and a controller. The controller is configured to generate a test code by dividing a test sequence in a unit of n-bits. The data driver is configured to receive the generated test code and output one of input voltages to a device under test as a test signal based on the generated test code. A storage device stores a test sequence.
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公开(公告)号：US10346570B2
公开(公告)日：2019-07-09
申请号：US15328321
申请日：2015-07-22
摘要： A method for determining system reliability of a logic circuit, wherein a functional component model for design/simulation of a circuit model of the logic circuit is created, where functional components model are expanded by adding an associated power model, a temperature model, and a reliability, where the logic circuit is constructed with expanded model components and, based on simulation of the logic circuit aided by the constructed circuit model, a functional, a power-dependent, and a temperature-dependent behavior and a temperature-dependent failure rate are derived for each component in a component specific manner for a specified application case, and where in addition to the functional behavior, a power and temperature behavior and a total failure rate can be determined simply and dynamically, based on the derived data and dependent on temperature and simulation time for the logic circuit for the specified application case.
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公开(公告)号：US10346259B2
公开(公告)日：2019-07-09
申请号：US13787488
申请日：2013-03-06
摘要： A Remote Metadata Center provides Distaster Recovery (DR) testing and metadata backup services to multiple business organizations. Metadata associated with local data backups performed at business organizations is transmitted to the Remote Metadata Center. Corresponding backup data is stored in a data storage system that is either stored locally at the business organization or at a data storage facility that is at a different location than the Remote Metadata Center and the business organization. DR testing can be staged from the Remote Data Center using the metadata received and optionally with assistance from an operator at the business organization and/or the data storage facility.
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公开(公告)号：US10324815B2
公开(公告)日：2019-06-18
申请号：US15432584
申请日：2017-02-14
发明人： Erez Barak , Oz D. Hershkovitz , Gilad Merran , Eyal Naor
摘要： Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.
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100.发明授权公开(公告)号：US10268556B2
公开(公告)日：2019-04-23
申请号：US15654032
申请日：2017-07-19
IPC分类号： G06F17/50 , G06F11/26 , G06F11/263
摘要： The present disclosure relates to system(s) and method(s) for simulation results analysis and failures debug using a Descriptive Tracking Header. The method may comprise processing a set of input packets by a Design Under Verification or System Under Verification (DUV/SUV) and mimicking, by a prediction unit corresponding to the DUV/SUV, functionality of the DUV/SUV. The prediction unit may be a part of a testbench and is configured to process a set of input packets to predict a set of expected output packets. In one embodiment, each expected output packet from the set of expected output packets may be attached with a Descriptive Tracking Header. The Descriptive Tracking Header corresponds to metadata associated with the expected output packet. The Descriptive Tracking Header is further updated based on the result of the comparison of the expected output packet against the corresponding actual output packet and used for the generation of simulation results summary for the purpose of simulation results analysis and failures debug.
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