公开(公告)号：US20240202001A1

公开(公告)日：2024-06-20

申请号：US18067016

申请日：2022-12-16

申请人： EDGECORTIX INC

发明人： Jens HUTHMANN ,  Sakyasingha DASGUPTA ,  Nikolay NEZ

IPC分类号： G06F9/38 ,  G06F5/01 ,  G06F7/32

CPC分类号： G06F9/3838 ,  G06F5/01 ,  G06F7/32 ,  G06F9/3855 ,  G06F9/3861

摘要： Sequence partition based schedule optimization is performed by generating a sequence and a schedule based on the sequence, dividing the sequence into a plurality of sequence partitions based on the schedule and the data dependency graph, each sequence partition including a portion of the plurality of instructions and a portion of the plurality of buffers, performing, for each sequence partition, a plurality of partition optimizing iterations, and merging the plurality of sequence partitions to produce a merged schedule.

公开(公告)号：US20240201998A1

公开(公告)日：2024-06-20

申请号：US18083185

申请日：2022-12-16

申请人： Microsoft Technology Licensing, LLC

发明人： Ahmed ABULILA ,  Rami Mohammad AL SHEIKH ,  Daren Eugene STREETT ,  Michael Scott MCILVAINE

IPC分类号： G06F9/38 ,  G06F12/0811 ,  G06F12/0875

CPC分类号： G06F9/3806 ,  G06F12/0811 ,  G06F12/0875 ,  G06F2212/27 ,  G06F2212/452

摘要： Performing storage-free instruction cache hit prediction is disclosed herein. In some aspects, a processor comprises an instruction cache hit prediction circuit that is configured to detect that a first access by a branch predictor circuit to a branch target buffer (BTB) for a first instruction in an instruction stream results in a miss on the BTB. In response to detecting the miss, the instruction cache hit prediction circuit is further configured to generate a first instruction cache prefetch request for the first instruction. The instruction cache hit prediction circuit is also configured to transmit the first instruction cache prefetch request to a prefetcher circuit.

公开(公告)号：US12014183B2

公开(公告)日：2024-06-18

申请号：US17949904

申请日：2022-09-21

申请人： Intel Corporation

发明人： John Wiegert ,  Joydeep Ray ,  Timothy Bauer ,  James Valerio

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/355 ,  G06F15/78

CPC分类号： G06F9/3887 ,  G06F9/355 ,  G06F15/7839 ,  G06F9/30036 ,  G06F9/30043

摘要： Embodiments described herein provide a technique to decompose 64-bit per-lane virtual addresses to access a plurality of data elements on behalf of a multi-lane parallel processing execution resource of a graphics or compute accelerator. The 64-bit per-lane addresses are decomposed into a base address and a plurality of per-lane offsets for transmission to memory access circuitry. The memory access circuitry then combines the base address and the per-lane offsets to reconstruct the per-lane addresses.

公开(公告)号：US12013809B2

公开(公告)日：2024-06-18

申请号：US17483395

申请日：2021-09-23

申请人： Beijing Tsingmicro Intelligent Technology Co., Ltd.

发明人： Peng Ouyang ,  Yaxue Zhang

IPC分类号： G06F15/80 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F15/80 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3867

摘要： A computing array includes a plurality of process element groups, and each of the plurality of the process element groups includes four process elements arranged in two rows and two columns and a merging unit. Each of the four process elements includes an input subunit; a fetch and decode subunit configured to obtain and compile the instruction to output a logic computing type; an operation subunit configured to obtain computing result data according to the logic computing type and the operation data; an output subunit configured to output the computing result data. The merging unit is connected to the output subunit of each of the four process elements, and configured to receive the computing result data output by the output subunit of each of the four process elements, merge the computing result data and output the merged computing result data.

公开(公告)号：US20240192985A1

公开(公告)日：2024-06-13

申请号：US18585018

申请日：2024-02-22

申请人： Nintex USA, Inc.

发明人： Joshua Joo Hou Tan ,  Alain Marie Patrice Gentilhomme

IPC分类号： G06F9/48 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F9/54

CPC分类号： G06F9/485 ,  G06F9/3005 ,  G06F9/3836 ,  G06F9/5044 ,  G06F9/505 ,  G06F9/546

摘要： Disclosed here are systems and methods that allow users, upon detecting errors within a running workflow, to either 1) pause the workflow and directly correct its design before resuming the workflow, or 2) pause the workflow, correct the erred action within the workflow, resume running the workflow, and afterwards apply the corrections to the design of the workflow. The disclosure comprises functionality that pauses a single workflow and other relevant workflows as soon as the error is detected and while it is corrected. The disclosed systems and methods improve communication technology between the networks and servers of separate parties relevant and/or dependent on successful execution of other workflows.

公开(公告)号：US20240192962A1

公开(公告)日：2024-06-13

申请号：US18444695

申请日：2024-02-18

申请人： GSI Technology Inc.

发明人： Avidan AKERIB

IPC分类号： G06F9/38 ,  G06F7/544 ,  G06F9/30

CPC分类号： G06F9/3893 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30079

摘要： A unit for accumulating a plurality of multiplied bit values includes a first row and a second row of input units, a bit-wise multiplier and a bit-wise accumulator. The first row receives a pipeline of the bits of a multiplicand A and the second row, to the left of the first row, receives a pipeline of the bits of a multiplicand B. The bit-wise multiplier, below the first row of input units, includes multiplier bit-line processors formed into rows and columns. Some rows of the bit-wise multiplier bit-wise multiplies bits of a current multiplicand A with one bit of a current multiplicand B and some rows of the bit-wise multiplier handle sum and carry values between the bits. The bit-wise accumulator, to the right of the bit-wise multiplier, includes a column of accumulator bit-line processors. Each accumulator bit-line processor accumulates output of a row of the bit-wise multiplier.

公开(公告)号：US20240192960A1

公开(公告)日：2024-06-13

申请号：US18502270

申请日：2023-11-06

申请人： SiFive, Inc.

发明人： Bruce Ableidinger

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30058

摘要： Systems and methods are disclosed for debug path profiling. For example, a processor pipeline may execute instructions. A debug trace circuitry may, responsive to an indication of a non-sequential execution of an instruction by the processor pipeline, generate a record including an address pair and one or more counter values. The address pair may include a first address corresponding to a first instruction before the non-sequential execution and a second address corresponding to a second instruction resulting in the non-sequential execution. The one or more counter values may indicate, for example, a count of instructions executed, a type of instruction executed, cache misses, cycles consumed by cache misses, translation lookaside buffer misses, cycles consumed by translation lookaside buffer misses, and/or processor stalls.

公开(公告)号：US12009034B2

公开(公告)日：2024-06-11

申请号：US16807065

申请日：2020-03-02

申请人： Micron Technology, Inc.

发明人： Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick Robert Khayat ,  Abdelhakim S. Alhussien

IPC分类号： G11C16/26 ,  G06F9/30 ,  G06F9/38 ,  G06F18/243 ,  H03M13/00 ,  H03M13/01

CPC分类号： G11C16/26 ,  G06F9/30021 ,  G06F9/30101 ,  G06F9/3804 ,  G06F18/24323 ,  H03M13/015 ,  H03M13/612

摘要： A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.

公开(公告)号：US12008376B2

公开(公告)日：2024-06-11

申请号：US17691212

申请日：2022-03-10

申请人： Hitachi, Ltd.

发明人： Keiko Ohkubo ,  Yu Nakata

IPC分类号： G06F9/38 ,  G06F9/48 ,  G06F9/50

CPC分类号： G06F9/3887 ,  G06F9/4862 ,  G06F9/5038 ,  G06F9/5077

摘要： One or more information processing apparatuses to process information are provided. The information processing apparatus includes: a division function that divides processing information into a plurality of pieces, under a division condition that designates parallel processing among the information processing apparatuses, the processing information indicating a data processing procedure from a plurality of start points to one or more end points; a determination function that uniquely determines an assignee of each piece of the processing information divided by the division function, as any of the information processing apparatuses; and an execution function that executes a process in the information processing apparatus determined by the determination function.

公开(公告)号：US12008369B1

公开(公告)日：2024-06-11

申请号：US17652501

申请日：2022-02-25

申请人： Apple Inc.

发明人： John D. Pape ,  Skanda K. Srinivasa ,  Francesco Spadini ,  Brian T. Mokrzycki

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/3001 ,  G06F9/30058 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3838 ,  G06F9/3858 ,  G06F9/3861

摘要： Techniques are disclosed that relate to executing fused instructions. A processor may include a decoder circuit and a load/store circuit. The decoder circuit may detect a load/store instruction to load a value from a memory and detect a non-load/store instruction that depends on the value to be loaded. The decoder circuit may fuse the load/store instruction and the non-load/store instruction such that one or more operations that the non-load/store instruction is defined to perform are to be executed within the load/store circuit. The load/store circuit may receive an indication of the fused load/store and non-load/store instructions and then execute one or more operations of the load/store instruction and the one or more operations of the non-load/store instruction using a circuit included in the load/store circuit.