公开(公告)号：US20240169663A1

公开(公告)日：2024-05-23

申请号：US17989548

申请日：2022-11-17

Applicant: Arm Limited

Inventor： Tord Kvestad Øygard ,  Philip Carlos Garcia ,  Sandeep Kakarlapudi

IPC: G06T15/40 ,  G06T15/00

CPC classification number: G06T15/405 ,  G06T15/005

Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output.

公开(公告)号：US20240169649A1

公开(公告)日：2024-05-23

申请号：US18509676

申请日：2023-11-15

Applicant: Arm Limited

Inventor： Ole Magnus Ruud ,  Per Kristian Kjøll

IPC: G06T15/00 ,  G06F9/48 ,  G06T15/40

CPC classification number: G06T15/005 ,  G06F9/4881 ,  G06T15/40

Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. Passes from different tiles can be interleaved.

公开(公告)号：US20240169645A1

公开(公告)日：2024-05-23

申请号：US18509432

申请日：2023-11-15

Applicant: Arm Limited

Inventor： Tord Kvestad Øygard ,  Olof Henrik Uhrenholt

IPC: G06T15/00 ,  G06T11/40

CPC classification number: G06T15/005 ,  G06T11/40

Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence of primitives, the visibility information being usable to determine whether or not fragments for a primitive in the sequence of primitives should subsequently be processed further for the render output, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. Processing of one or more vertex attributes may be omitted during the first, pre-pass operation.

公开(公告)号：US20240169619A1

公开(公告)日：2024-05-23

申请号：US18509687

申请日：2023-11-15

Applicant: Arm Limited

Inventor： Ole Magnus Ruud ,  Sandeep Kakarlapudi ,  Tord Kvestad Øygard ,  Per Kristian Kjøll ,  Toni Viki Brkic

IPC: G06T11/40 ,  G06T1/20

CPC classification number: G06T11/40 ,  G06T1/20

Abstract: When performing tile-based rendering a first, pre-pass operation in which primitives in a sequence of primitives for a tile are processed to determine visibility information for the sequence, the visibility information being usable to determine whether fragments for a primitive in the sequence should subsequently be processed further, is performed. Thereafter a second, main pass operation is performed in which the further processing of fragments for primitives that were processed during the first, pre-pass operation is controlled based on the determined visibility information for the sequence of primitives, such that for fragments for which the visibility information indicates that the fragments should not be processed further for the render output some or all of the processing during the second, main pass is omitted. The visibility information indicates which primitives should be rendered for which sampling positions of the render output in a hierarchical manner.

公开(公告)号：US20240169612A1

公开(公告)日：2024-05-23

申请号：US18509277

申请日：2023-11-14

Applicant: Arm Limited

Inventor： Rafal Stepuch ,  Frank Klaeboe Langtind

IPC: G06T11/20 ,  G06T1/60

CPC classification number: G06T11/20 ,  G06T1/60 ,  G06T2210/12

Abstract: When processing primitives in a tile-based graphics processing system in which a render output is sub-divided into a plurality of tiles for rendering, before a primitive is written to a primitive list corresponding to a region of the render output, it is first determined whether the primitive can be grouped with one or more previous primitives based on the set of regions of the render output that primitive covers relative to the set of regions of the render output that one or more previous primitives cover. When it is determined that the primitive can be grouped with one or more previous primitives, the primitive is added to a group (i.e. grouped) with the one or more previous primitives. The grouped primitives are then later written together to one or more primitive lists, in a single primitive list write cycle.

公开(公告)号：US20240169474A1

公开(公告)日：2024-05-23

申请号：US18503894

申请日：2023-11-07

Applicant: Arm Limited

Inventor： Andreas Due Engh-Halstvedt ,  Frank Klaeboe Langtind

IPC: G06T1/60 ,  G06F12/02 ,  G06T11/20

CPC classification number: G06T1/60 ,  G06F12/023 ,  G06T11/20

Abstract: When preparing and storing a primitive list in a tile-based graphics processing system, a first block of memory space is allocated for storing the primitive list. When there is insufficient space in the first block of memory space to store all of the graphics primitives for the primitive list, a next block of memory space to be used for storing the primitive list is allocated for storing the primitive list. An indication of the location in memory of the allocated next block of memory space is written at the beginning of the first block of memory space.

公开(公告)号：US11989425B2

公开(公告)日：2024-05-21

申请号：US17759426

申请日：2020-12-21

Applicant: Arm Limited

Inventor： Thomas Christopher Grocutt

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/14

CPC classification number: G06F3/0622 ,  G06F3/0637 ,  G06F3/0673 ,  G06F12/1466

Abstract: A technique for controlling access to memory mapped control registers. The apparatus has processing circuitry for executing program code to perform data processing operations, and a set of memory mapped control registers for storing control information used to control operation of the processing circuitry. Further, a lockdown register used to store a lockdown value. The processing circuitry is arranged to execute store instructions to perform write operations to a memory address space. The processing circuitry is arranged to prevent a write operation being performed to change the control information in the memory mapped control registers. This significantly reduces the prospect of an attacker seeking to exploit a software vulnerability to change the control information in the memory mapped control registers.

公开(公告)号：US11989134B2

公开(公告)日：2024-05-21

申请号：US17907178

申请日：2021-03-08

Applicant: ARM LIMITED

Inventor： Yuval Elad ,  Jason Parker ,  Richard Roy Grisenthwaite ,  Simon John Craske ,  Alexander Donald Charles Chadwick

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/10

CPC classification number: G06F12/10 ,  G06F3/0622 ,  G06F3/0637 ,  G06F3/0673

Abstract: An apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.

公开(公告)号：US11983792B2

公开(公告)日：2024-05-14

申请号：US17662565

申请日：2022-05-09

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt ,  Toni Viki Brkic ,  Edward Hardy

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T15/005

Abstract: A graphics processor comprising a rasteriser, a renderer, and a fragment dependency manager, and a method of operating a graphics processor. The fragment dependency manager is operable to maintain plural queues, where each queue corresponds to a respective set of plural sets of one or more sampling points that an array of sampling points is divided into, and wherein each queue entry is indicative of one or more fragments that when processed by the renderer will produce rendered fragment data for one or more of the sampling points of the set of one or more sampling points to which the queue corresponds.

公开(公告)号：US11983533B2

公开(公告)日：2024-05-14

申请号：US17851266

申请日：2022-06-28

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Alexander Cole Shulyak ,  Yasuo Ishii ,  Houdhaifa Bouzguarrou

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30058 ,  G06F9/3861

Abstract: There is provided a data processing apparatus comprising history storage circuitry that stores sets of behaviours of helper instructions for a control flow instruction. Pointer storage circuitry stores pointers, each associated with one of the sets. The behaviours in the one of the sets are indexed according to one of the pointers associated with that one of the sets. Increment circuitry increments at least some of the pointers in response to an increment event and prediction circuitry determines a predicted behaviour of the control flow instruction using one of the sets of behaviours.