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    Method for biasing columns of a pixel array and associated device
    102.
    发明授权
    Method for biasing columns of a pixel array and associated device 有权

    公开(公告)号：US10728481B2

    公开(公告)日：2020-07-28

    申请号：US16165586

    申请日：2018-10-19

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Nicolas Moeneclaey

    IPC: H04N5/3745 ,  H04N5/378 ,  H04N5/357

    Abstract: A method is disclosed for operating an imaging device having a matrix of pixels arranged in rows and columns. A polarization voltage is generated on a gate of a main MOS transistor that is connected as diode. The main MOS transistor is coupled between a power supply voltage and a ground circuit. Prior to reading the pixels of a row of the matrix, a plurality of first capacitors are charged with the polarization voltage. The first capacitors are coupled between the gate of the main transistor and a ground node. Upon reading the pixels of the row, the first capacitors are discharged on respective gates of auxiliary transistors coupled between the columns and the ground node so as to switch on the auxiliary transistors and deliver a substantially identical polarization current to each column.

    Method, device and article to test digital circuits
    108.
    发明授权
    Method, device and article to test digital circuits 有权

    公开(公告)号：US10578672B2

    公开(公告)日：2020-03-03

    申请号：US14986053

    申请日：2015-12-31

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： David Jacquet ,  Didier Fuin

    IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185

    Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.

    Clock synchronization device
    109.
    发明授权
    Clock synchronization device 有权

    公开(公告)号：US10530563B2

    公开(公告)日：2020-01-07

    申请号：US15898816

    申请日：2018-02-19

    Applicant: STMicroelectronics (Grenoble 2) SAS

    Inventor： Etienne Cesar

    IPC: H04L7/033 ,  H03L7/085 ,  H03L7/099

    Abstract: In an embodiment, a clock synchronizing circuit includes: a phase comparator including a first circuit having a first input configured to receive a data signal; and a second circuit. The first circuit is configured to detect edges of the data signal. The second circuit includes a clock generator configured to generate a clock signal with adjustable frequency, where the phase comparator is configured to compare, after detecting an edge of the data signal, an edge of the data signal with an edge of the clock signal, and where the second circuit is configured to modify a frequency of the clock signal as a function of an output signal of the phase comparator.

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