公开(公告)号：US20140004666A1

公开(公告)日：2014-01-02

申请号：US13536829

申请日：2012-06-28

Applicant: Aaron D. FRANKLIN ,  Shu-Jen HAN ,  George S. TULEVSKI

Inventor： Aaron D. FRANKLIN ,  Shu-Jen HAN ,  George S. TULEVSKI

IPC: H01L21/336 ,  B82Y40/00

CPC classification number: H01L29/7827 ,  B82Y10/00 ,  B82Y40/00 ,  B82Y99/00 ,  H01L51/0048 ,  H01L51/0049 ,  H01L51/0558

Abstract: A transistor device is fabricated, in one embodiment, by providing an insulator on a substrate and forming a gate embedded in the insulator. A dielectric material is deposited over the gate and insulator forming a dielectric layer. A channel comprising carbon nanotubes is formed on the dielectric layer over the gate. A self-assembled monolayer is formed over at least the channel.

Abstract translation: 在一个实施例中，通过在衬底上提供绝缘体并形成嵌入绝缘体中的栅极来制造晶体管器件。 介电材料沉积在形成电介质层的栅极和绝缘体上。 在栅极上的介电层上形成包含碳纳米管的通道。 至少在通道上形成自组装单层。

公开(公告)号：US08604519B2

公开(公告)日：2013-12-10

申请号：US13487473

申请日：2012-06-04

Applicant: Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

IPC: H01L29/66 ,  H01L21/02 ,  H01L31/06

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/78681

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.

Abstract translation: 场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置限定在分层半导体晶片上。 分层半导体晶片优选地包括III-V半导体表面层，例如砷化镓（GaAs）和掩埋层，例如砷化铝（AlAs）。 掩埋层的一部分至少在FET源极/漏极区下面被转换为电介质材料，例如氧化铝（AlO）。 转换的电介质材料可以在FET下完全延伸。 源极/漏极触点形成在掩埋层中的电介质材料上方的FET上。

公开(公告)号：US08519454B2

公开(公告)日：2013-08-27

申请号：US13075443

申请日：2011-03-30

Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L29/76 ,  H01L21/338 ,  H01L21/84

CPC classification number: H01L29/4966 ,  H01L29/66545 ,  H01L29/7843

Abstract: Processes for metal fill in replacement metal gate integration schemes and resultant devices are provided herein. The method includes forming a dummy gate on a semiconductor substrate. The dummy gate includes forming a metal layer between a first material and a second material. The method further includes partially removing the dummy gate to form an opening bounded by a spacer material. The method further includes forming a recess in the spacer material to widen a portion of the opening. The method further includes removing a remaining portion of the dummy gate through the opening to form a trench having the recess forming an upper portion thereof. The method further includes filling the trench and the recess with a replacement metal gate stack.

Abstract translation: 本文提供了用于替换金属栅极集成方案和所得器件的金属填充工艺。 该方法包括在半导体衬底上形成虚拟栅极。 虚拟门包括在第一材料和第二材料之间形成金属层。 该方法还包括部分地去除伪栅极以形成由间隔物材料限定的开口。 该方法还包括在间隔物材料中形成凹槽以加宽开口的一部分。 该方法还包括通过开口去除虚拟栅极的剩余部分以形成具有形成其上部的凹部的沟槽。 该方法还包括用替换的金属栅极堆叠填充沟槽和凹部。

公开(公告)号：US08466493B2

公开(公告)日：2013-06-18

申请号：US13074854

申请日：2011-03-29

Applicant: Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

Inventor： Cheng-Wei Cheng ,  Shu-Jen Han ,  Kuen-Ting Shiu

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/4763

CPC classification number: H01L29/0847 ,  H01L29/0653 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/78681

Abstract: Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaAs), and a buried layer, e.g., Aluminum Arsenide (AlAs). Portions of the buried layer are converted to dielectric material, e.g., Aluminum Oxide (AlO), at least beneath FET source/drain regions. The converted dielectric material may extend completely under the FET. Source/drain contacts are formed to FETs above the dielectric material in the buried layer.

Abstract translation: 场效应晶体管（FET），包括FET的集成电路（IC）芯片，以及形成FET和IC的方法。 FET位置限定在分层半导体晶片上。 分层半导体晶片优选地包括III-V半导体表面层，例如砷化镓（GaAs）和掩埋层，例如砷化铝（AlAs）。 掩埋层的一部分至少在FET源极/漏极区下面被转换为电介质材料，例如氧化铝（AlO）。 转换的电介质材料可以在FET下完全延伸。 源极/漏极触点形成在掩埋层中的电介质材料上方的FET上。

公开(公告)号：US20130143769A1

公开(公告)日：2013-06-06

申请号：US13310194

申请日：2011-12-02

Applicant: Ali Afzali-Ardakani ,  Shu-jen Han ,  Amal Kasry ,  Ahmed Maarouf ,  Glenn J. Martyna ,  Razvan Nistor ,  Hsinyu Tsai

Inventor： Ali Afzali-Ardakani ,  Shu-jen Han ,  Amal Kasry ,  Ahmed Maarouf ,  Glenn J. Martyna ,  Razvan Nistor ,  Hsinyu Tsai

IPC: C40B40/04 ,  C40B50/14 ,  C40B40/00 ,  B82Y99/00

CPC classification number: G01N33/531 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/194 ,  G01N33/5308 ,  G01N33/54373 ,  G01N33/54393 ,  G01N33/551 ,  G01N2400/00 ,  H01L21/30

Abstract: A graphene nanomesh based charge sensor and method for producing a graphene nanomesh based charge sensor. The method includes generating multiple holes in graphene in a periodic way to create a graphene nanomesh with a patterned array of multiple holes, passivating an edge of each of the multiple holes of the graphene nanomesh to allow for functionalization of the graphene nanomesh, and functionalizing the passivated edge of each of the multiple holes of the graphene nanomesh with a chemical compound that facilitates chemical binding of a receptor of a target molecule to the edge of one or more of the multiple holes, allowing the target molecule to bind to the receptor, causing a charge to be transferred to the graphene nanomesh to produce a graphene nanomesh based charge sensor for the target molecule.

Abstract translation: 一种基于石墨烯纳米薄膜的电荷传感器和用于生产基于石墨烯纳米薄膜的电荷传感器的方法。 该方法包括以周期性方式在石墨烯中产生多个孔以产生具有多个孔的图案化阵列的石墨烯纳米粒子，钝化石墨烯纳米粒子的多个孔中的每一个的边缘以允许石墨烯纳米粒子的官能化，并使 石墨烯纳米粒子的多个孔的每个的钝化边缘具有促进靶分子的受体与多个孔中的一个或多个的边缘的化学结合的化学化合物，允许靶分子结合受体，导致 将转移到石墨烯纳米片上的电荷以产生用于靶分子的基于石墨烯纳米膜的电荷传感器。

公开(公告)号：US08445371B2

公开(公告)日：2013-05-21

申请号：US12755752

申请日：2010-04-07

Applicant: Dechao Guo ,  Wilfried E. A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Dechao Guo ,  Wilfried E. A. Haensch ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L21/3205

CPC classification number: H01L21/28008 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/76897 ,  H01L29/517 ,  H01L29/66507 ,  H01L29/66545

Abstract: A method of forming a gate structure with a self-aligned contact is provided and includes sequentially depositing a sacrificial layer and a secondary layer onto poly-Si disposed at a location of the gate structure, encapsulating the sacrificial layer, the secondary layer and the poly-Si, removing the sacrificial layer through openings formed in the secondary layer and forming silicide within at least the space formally occupied by the sacrificial layer.

公开(公告)号：US20130082243A1

公开(公告)日：2013-04-04

申请号：US13610381

申请日：2012-09-11

Applicant: Shu-Jen Han ,  Alberto Valdes Garcia

Inventor： Shu-Jen Han ,  Alberto Valdes Garcia

IPC: H01L29/78 ,  B82Y99/00

CPC classification number: H01L29/66742 ,  H01L29/42384 ,  H01L29/7781 ,  H01L29/78603 ,  H01L29/78636 ,  H01L29/78684

Abstract: A device with reduced gate resistance includes a gate structure having a first conductive portion and a second conductive portion formed in electrical contact with the first conductive portion and extending laterally beyond the first conductive portion. The gate structure is embedded in a dielectric material and has a gate dielectric on the first conductive portion. A channel layer is provided over the first conductive portion. Source and drain electrodes are formed on opposite end portions of a channel region of the channel layer. Methods for forming a device with reduced gate resistance are also provided.

Abstract translation: 具有降低的栅极电阻的器件包括具有第一导电部分和形成为与第一导电部分电接触并且横向延伸超过第一导电部分延伸的第二导电部分的栅极结构。 栅极结构嵌入电介质材料中，并且在第一导电部分上具有栅极电介质。 沟道层设置在第一导电部分上。 源极和漏极形成在沟道层的沟道区的相对端部上。 还提供了形成栅极电阻降低的器件的方法。

公开(公告)号：US20130015428A1

公开(公告)日：2013-01-17

申请号：US13610089

申请日：2012-09-11

Applicant: Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

Inventor： Zhihong Chen ,  Aaron Daniel Franklin ,  Shu-Jen Han

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L51/0048 ,  B82Y10/00 ,  H01L51/0558 ,  Y10S977/742 ,  Y10S977/938

Abstract: Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.

Abstract translation: 提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。 一方面，提供一种晶体管器件。 晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和 第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。 还提供了一种制造晶体管器件的方法。

公开(公告)号：US08338258B2

公开(公告)日：2012-12-25

申请号：US12625827

申请日：2009-11-25

Applicant: Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

Inventor： Dechao Guo ,  Shu-Jen Han ,  Pranita Kulkarni ,  Philip J. Oldiges

IPC: H01L21/336

CPC classification number: H01L29/1054 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/66772 ,  H01L29/78687

Abstract: A method of fabricating an embedded stressor within a semiconductor structure and a semiconductor structure including the embedded stressor includes forming forming a dummy gate stack over a substrate of stressor material, anistropically etching sidewall portions of the substrate subjacent to the dummy gate stack to form the embedded stressor having angled sidewall portions, forming conductive material onto the angled sidewall portions of the embedded stressor, removing the dummy gate stack, planarizing the conductive material, and forming a gate stack on the conductive material.

Abstract translation: 一种在半导体结构内制造嵌入式应力器的方法以及包括所述嵌入式应力器的半导体结构的方法包括在所述应力源材料的衬底上形成形成虚拟栅极叠层的方法，将所述衬底的与所述虚拟栅极堆叠相邻的衬底的侧壁部分， 应力器具有成角度的侧壁部分，将导电材料形成在嵌入式应力源的成角度的侧壁部分上，去除虚拟栅极堆叠，平坦化导电材料，以及在导电材料上形成栅极叠层。

公开(公告)号：US08338256B2

公开(公告)日：2012-12-25

申请号：US12832829

申请日：2010-07-08

Applicant: Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

Inventor： Josephine B. Chang ,  Dechao Guo ,  Shu-Jen Han ,  Chung-Hsun Lin

IPC: H01L21/336 ,  H01L29/76

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L2029/7858

Abstract: A multi-gate transistor having a plurality of sidewall contacts and a fabrication method that includes forming a semiconductor fin on a semiconductor substrate and etching a trench within the semiconductor fin, depositing an oxide material within the etched trench, and etching the oxide material to form a dummy oxide layer along exposed walls within the etched trench; and forming a spacer dielectric layer along vertical sidewalls of the dummy oxide layer. The method further includes removing exposed dummy oxide layer in a channel region in the semiconductor fin and beneath the spacer dielectric layer, forming a high-k material liner along sidewalls of the channel region in the semiconductor fin, forming a metal gate stack within the etched trench, and forming a plurality of sidewall contacts within the semiconductor fin along adjacent sidewalls of the dummy oxide layer.

Abstract translation: 一种具有多个侧壁触点的多栅极晶体管及其制造方法，包括在半导体衬底上形成半导体鳍片并蚀刻半导体鳍片内的沟槽，在蚀刻沟槽内沉积氧化物材料，并蚀刻氧化物材料以形成 沿着蚀刻沟槽内的暴露壁的虚拟氧化物层; 以及沿所述虚拟氧化物层的垂直侧壁形成间隔电介质层。 该方法还包括去除半导体鳍片中的沟道区域中的暴露的虚拟氧化物层并且在间隔物电介质层下方形成沿着半导体鳍片中的沟道区域的侧壁形成高k材料衬垫，在蚀刻 沟槽，并且在半导体鳍片内沿虚拟氧化物层的相邻侧壁形成多个侧壁接触。