POWER SEMICONDUCTOR DEVICE
    101.
    发明申请

    公开(公告)号:US20250081553A1

    公开(公告)日:2025-03-06

    申请号:US18388870

    申请日:2023-11-13

    Abstract: A power semiconductor device, including a cell region, a transition region, and a terminal region. The transition region is located between the cell region and the terminal region of the device. A first conduction type substrate, a first conduction type epitaxial layer located above the first conduction type substrate, and a first conduction type buffer layer located in the first conduction type epitaxial layer are jointly arranged at the bottoms of the cell region, the transition region, and the terminal region of the device. In a high-current application, since the cell region occupies the largest area of a chip, in a case that breakdown can occur in the cell region and the current can be discharged through the cell region. On the basis of ensuring the BV of the terminal region, a silicon layer step is formed by elevating the position of a top structure of the terminal region.

    Multi-level gate driver applied to SiC MOSFET

    公开(公告)号:US12199150B2

    公开(公告)日:2025-01-14

    申请号:US17848422

    申请日:2022-06-24

    Abstract: A multi-level gate driver applied to the SiC metal-oxide-semiconductor field-effect transistor (MOSFET) includes three parts: the SiC MOSFET information detection circuit, the signal level shifting circuit, and the segmented driving circuit. The SiC MOSFET information detection circuit includes the SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit. The segmented driving circuit includes a turn-on segmented driving circuit and a turn-off segmented driving circuit. The SiC MOSFET drain-source voltage detection circuit and the SiC MOSFET drain-source current detection circuit process a drain-source voltage and a drain-source current during the SiC MOSFET's switching as enable signals for segmented driving; the signal level shifting circuit transfers enable signals required by the segmented driving circuit to the suitable power supply rail; and the SiC MOSFET turn-on segmented driving circuit and the turn-off segmented driving circuit select suitable driving currents.

    Scattering aperture imaging method and device, system, and storage medium

    公开(公告)号:US12181572B1

    公开(公告)日:2024-12-31

    申请号:US18652208

    申请日:2024-05-01

    Abstract: Provided are a scattering aperture imaging method and a device, a system and a storage medium. The method mainly includes four steps of scattering point position estimation, azimuth resampling, range compensation and synthetic aperture radar imaging. A phased array radar with a fixed position is used for NLOS imaging, and the radar can control a beam to scan in space, which is equivalent to a scattering aperture moving along a relay surface. Therefore, the method can realize converting NLOS imaging into LOS synthetic aperture radar imaging, which can be suitable for the situation that a relay surface is rough and the relay surface with more complicated surface condition, thus widening the application range of radar NLOS imaging.

    LATERAL POWER SEMICONDUCTOR DEVICE
    106.
    发明申请

    公开(公告)号:US20240395930A1

    公开(公告)日:2024-11-28

    申请号:US18382561

    申请日:2023-10-23

    Abstract: A lateral power semiconductor device is provided and includes a second doping type substrate, a first doping type buried layer, a second doping type epitaxial layer, a first doping type drift area, a second doping type first body area, a first doping type drain area, a first doping type source area, a second doping type second body area, a dielectric layer, a control gate, a body electrode, second doping type polysilicon and first doping type polysilicon. The control gate is led out and connected to different potentials; when the device is in an off state, the control gate is connected to a low potential to assist the drift area in depletion; and when the device is in an on state, the control gate is connected to a high potential, and more carriers are induced on a silicon surface below the control gate.

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