公开(公告)号：US5962903A

公开(公告)日：1999-10-05

申请号：US730949

申请日：1996-10-16

申请人： Hung-Cheng Sung ,  Ling Chen

发明人： Hung-Cheng Sung ,  Ling Chen

IPC分类号： H01L27/102 ,  H01L29/861 ,  H01L29/04 ,  H01L29/41

CPC分类号： H01L27/1021 ,  Y10S257/926

摘要： A Mask ROM and a method of manufacture of a Mask ROM on a semiconductor substrate comprises formation of a first plurality of conductor lines in a first array. A dielectric layer is formed upon the device with a matrix of openings therein in line with the first array. The openings expose the surface of the first conductor lines. Semiconductor diodes are formed in the matrix of openings in contact with the first conductor lines. A second plurality of conductor lines are formed on the surface of the dielectric layer in a second array of conductor lines orthogonal to the first plurality of conductor lines in the first array. A second plurality of conductor lines is aligned with the matrix and is in contact with the upper ends of the semiconductor diodes.

摘要翻译： 掩模ROM和在半导体衬底上制造掩模ROM的方法包括以第一阵列形成第一多条导体线。 电介质层在其上具有与第一阵列一致的开口矩阵的器件上形成。 开口露出第一导体线的表面。 半导体二极管形成在与第一导线接触的开口矩阵中。 在与第一阵列中的第一多个导体线正交的导体线的第二阵列中，在电介质层的表面上形成第二多个导体线。 第二多个导体线与矩阵对准并且与半导体二极管的上端接触。

公开(公告)号：US5734607A

公开(公告)日：1998-03-31

申请号：US688069

申请日：1996-07-29

申请人： Hung-Cheng Sung ,  Ling Chen

发明人： Hung-Cheng Sung ,  Ling Chen

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L23/58

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： An integrated circuit EPROM memory device includes devices to which electrical connections are to be made. A tunnel oxide layer on a semiconductor substrate carries an array of gate stacks with sidewalls with trench spaces therebetween comprising wider drain trench spaces and narrower source trench spaces down to the tunnel oxide layer. Gate stacks include a doped polysilicon floating gate over the tunnel oxide layer, a dielectric layer over the floating gate, a polysilicon control gate over the dielectric layer covered by a silicon dioxide dielectric layer and a silicon nitride layer. Source/drain regions lie between the stacks with alternating source regions and drain regions below the trench spaces between the sidewalls. Spacers are adjacent to the sidewalls of the drain trench spaces. Spacer dielectric plugs fill source trench spaces. A blanket dielectric layer overlies the stacks and the spacer dielectric plugs. Bitlines extend across the stacks into contact with the drain regions through the drain trench spaces. The memory devices include a self-aligned bitline structure formed simultaneously with electrical contacts to the drains.

摘要翻译： 集成电路EPROM存储器件包括要进行电连接的器件。 半导体衬底上的隧道氧化物层带有具有其间沟槽空间的侧壁的栅极堆叠阵列，包括更宽的漏极沟槽空间和较窄的沟槽氧化物层的源极沟槽空间。 栅极堆叠包括在隧道氧化物层上的掺杂多晶硅浮置栅极，浮置栅极上的电介质层，在由二氧化硅介电层和氮化硅层覆盖的电介质层上的多晶硅控制栅极。 源极/漏极区域位于具有交替的源极区域和在侧壁之间的沟槽间隔之下的漏极区域的堆叠之间。 隔板与排水槽空间的侧壁相邻。 间隔绝缘塞填充源沟槽空间。 叠层介电层覆盖在叠层和间隔电介质塞之间。 位线延伸穿过堆叠，通过漏极沟槽空间与漏极区域接触。 存储器件包括与对漏极的电触点同时形成的自对准位线结构。

公开(公告)号：US20130307080A1

公开(公告)日：2013-11-21

申请号：US13472890

申请日：2012-05-16

申请人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

发明人： Yue-Der Chih ,  Jam-Wem Lee ,  Cheng-Hsiung Kuo ,  Tsung-Che Tsai ,  Ming-Hsiang Song ,  Hung-Cheng Sung ,  Roger Wang

IPC分类号： H01L27/088 ,  H01L21/04

CPC分类号： H01L21/823814 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/1083 ,  H01L29/36 ,  H01L29/423

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a metal oxide device. The metal oxide device includes first and second doped regions disposed within the substrate and interfacing in a channel region. The first and second doped regions are doped with a first type dopant. The first doped region has a different concentration of dopant than the second doped region. The metal oxide device further includes a gate structure traversing the channel region and the interface of the first and second doped regions and separating source and drain regions. The source region is formed within the first doped region and the drain region is formed within the second doped region. The source and drain regions are doped with a second type dopant. The second type dopant is opposite of the first type dopant.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性的半导体器件包括包括金属氧化物器件的衬底。 金属氧化物器件包括设置在衬底内的第一和第二掺杂区域，并且在沟道区域中连接。 第一和第二掺杂区掺杂有第一类掺杂剂。 第一掺杂区具有与第二掺杂区不同的掺杂浓度。 金属氧化物器件还包括穿过沟道区域的栅极结构以及第一和第二掺杂区域的界面以及分离源极和漏极区域。 源极区域形成在第一掺杂区域内，并且漏极区域形成在第二掺杂区域内。 源区和漏区掺杂有第二类掺杂剂。 第二种掺杂剂与第一种掺杂剂相反。

公开(公告)号：US20080258200A1

公开(公告)日：2008-10-23

申请号：US11785608

申请日：2007-04-19

申请人： Shih Wei Wang ,  Te-Hsun Hsu ,  Hung-Cheng Sung

发明人： Shih Wei Wang ,  Te-Hsun Hsu ,  Hung-Cheng Sung

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L27/115 ,  H01L29/42336

摘要： A semiconductor memory device includes a substrate, and a trench formed in the substrate. First and second floating gates, each associated with corresponding first and second memory cells, extend into the trench. Since the trench can be made relatively deep, the floating gates may be made relatively large while the lateral dimensions of the floating gates remains small. Moreover, the insulator thickness between the floating gate and a sidewall of the trench where a channel region is formed can be made relatively thick, even though the lateral extent of the memory cell is reduced. A programming gate extends into the trench between the first and second floating gates, and is shared, along with a source region, by the two memory cells.

摘要翻译： 半导体存储器件包括衬底和形成在衬底中的沟槽。 每个与对应的第一和第二存储器单元相关联的第一和第二浮动栅极延伸到沟槽中。 由于可以使沟槽相对较深，所以可以使浮动栅极相对较大，同时浮动栅极的横向尺寸保持较小。 此外，尽管存储单元的横向范围减小，浮栅和形成沟道区的沟槽的侧壁之间的绝缘体厚度可以做得相对较厚。 编程门延伸到第一和第二浮栅之间的沟槽中，并且与源区域一起被两个存储单元共享。

公开(公告)号：US07226828B2

公开(公告)日：2007-06-05

申请号：US10833179

申请日：2004-04-27

申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Te-Hsun Hsu

发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Te-Hsun Hsu

IPC分类号： H01L21/8238

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L22/34 ,  H01L27/11521 ,  H01L2924/0002 ,  H01L2924/00

摘要： A new method to form a floating gate isolation test structure in the manufacture of a memory device is achieved. The method comprises providing a substrate. A gate oxide layer is formed overlying the substrate. A floating gate conductor layer is deposited overlying the gate oxide layer. The floating gate conductor layer is patterned to expose the substrate for planned source regions. Ions are implanted into the exposed substrate to form the source regions. Contacting structures are formed to the source regions. Contacting structures are formed to the floating gate conductor layer.

摘要翻译： 实现了在制造存储器件中形成浮栅隔离测试结构的新方法。 该方法包括提供基底。 栅极氧化层形成在衬底上。 沉积栅极氧化物层的浮栅导体层。 图案化浮栅导体层以暴露用于计划源区的衬底。 将离子注入到暴露的基底中以形成源区。 接触结构形成于源区。 接触结构形成于浮栅导体层。

公开(公告)号：US07176083B2

公开(公告)日：2007-02-13

申请号：US10870774

申请日：2004-06-17

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

IPC分类号： H01L21/336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

公开(公告)号：US20070023822A1

公开(公告)日：2007-02-01

申请号：US11192669

申请日：2005-07-30

申请人： Hung-Cheng Sung ,  Te-Hsun Hsu ,  Shih-Wei Wang

发明人： Hung-Cheng Sung ,  Te-Hsun Hsu ,  Shih-Wei Wang

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L29/42324 ,  H01L29/66825

摘要： A programmable non-volatile memory (PNVM) device and method of forming the same compatible with CMOS logic device processes to improve a process flow, the PNVM device including a semiconductor substrate active area; a gate dielectric on the active area; a floating gate electrode on the gate dielectric; an inter-gate dielectric disposed over the floating gate electrode; and, a control gate damascene electrode extending through a dielectric insulating layer in electrical communication with the inter-gate dielectric, the control gate damascene electrode disposed over an upper portion of the floating gate electrode.

摘要翻译： 一种可编程非易失性存储器（PNVM）器件和形成与CMOS逻辑器件工艺兼容的方法，以改善工艺流程，PNVM器件包括半导体衬底有源区; 有源区上的栅极电介质; 栅极电介质上的浮栅电极; 设置在所述浮栅上的栅极间电介质; 以及延伸穿过与所述栅极间电介质电连通的介电绝缘层的控制栅极镶嵌电极，所述控制栅极镶嵌电极设置在所述浮栅电极的上部。

公开(公告)号：US20060203537A1

公开(公告)日：2006-09-14

申请号：US11078171

申请日：2005-03-11

申请人： Hung-Cheng Sung ,  Der-Shin Shyu

发明人： Hung-Cheng Sung ,  Der-Shin Shyu

IPC分类号： G11C11/00

CPC分类号： G11C11/16

摘要： Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.

摘要翻译： 确定存储单元写入电流的方法。 将第一参考电流施加到第一操作线以将存储器单元切换到第一状态。 第二参考电流被施加到穿过第一操作线的第二操作线，以将存储器单元切换到第二状态。 根据第一比率和第一参考电流获得第一写入电流。 根据第二比例和第二参考电流获得第二写入电流。 通过将第一写入电流施加到第一操作线并将第二写入电流施加到第二操作线来编程存储器单元。

公开(公告)号：US20060014345A1

公开(公告)日：2006-01-19

申请号：US10890673

申请日：2004-07-14

申请人： Te-Hsun Hsu ,  Hung-Cheng Sung

发明人： Te-Hsun Hsu ,  Hung-Cheng Sung

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A new method to form a split gate for a flash device in the manufacture of an integrated circuit device is achieved. The method comprises providing a substrate. A film is deposited overlying the substrate. The film comprises a second dielectric layer overlying a first dielectric layer with an electronic-trapping layer therebetween. A masking layer is deposited overlying the film. The masking layer and the film are patterned to expose a part of the substrate and to form a floating gate electrode comprising the electronic-trapping layer. An oxide layer is grown overlying the exposed part of the substrate. The masking layer is removed. A conductive layer is deposited overlying the oxide layer and the second dielectric layer. The conductive layer and the oxide layer are patterned to complete a control gate electrode comprising the conductive layer. The control gate electrode has a first part overlying the floating gate electrode and a second part not overlying the floating gate electrode.

摘要翻译： 实现了在制造集成电路器件中形成用于闪存器件的分离栅极的新方法。 该方法包括提供基底。 覆盖在衬底上的膜被沉积。 膜包括覆盖在第一电介质层之间的电子捕获层的第二电介质层。 掩模层沉积在膜上。 图案化掩模层和膜以暴露基板的一部分并形成包括电子捕获层的浮栅电极。 生长在衬底的暴露部分上的氧化物层。 去除掩模层。 沉积覆盖氧化物层和第二介电层的导电层。 图案化导电层和氧化物层以完成包括导电层的控制栅电极。 控制栅电极具有覆盖浮置栅电极的第一部分和不覆盖浮置栅电极的第二部分。

公开(公告)号：US20050282337A1

公开(公告)日：2005-12-22

申请号：US10870774

申请日：2004-06-17

申请人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

发明人： Der-Shin Shyu ,  Hung-Cheng Sung ,  Chen-Ming Huang

IPC分类号： H01L21/336 ,  H01L21/4763 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7885

摘要： An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.

摘要翻译： 一种嵌入式闪存单元结构，其包括结构，第一浮动栅极，其具有在所述结构上方的暴露侧壁，第二浮动栅极，具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极，至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物，在第二对间隔物之间​​的结构中的源极区域，源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门，并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。