公开(公告)号：US20090190425A1

公开(公告)日：2009-07-30

申请号：US12257739

申请日：2008-10-24

Applicant: Gil I. Winograd ,  Andreas Gotterba ,  Esin Terzioglu

Inventor： Gil I. Winograd ,  Andreas Gotterba ,  Esin Terzioglu

IPC: G11C7/00 ,  G11C7/06

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: A memory is provided that practices global read line sharing by including: a global read line, the memory being adapted to be pre-charge the global read line prior to a read operation; an I/O circuit to receive the global read line; and a plurality of sense amplifiers, each sense amplifier being multiplexed with respect to the global read line such that only a selected one of the sense amplifiers in the plurality is activated during a read operation to determine a bit decision, the memory being adapted to discharge the pre-charged global read line if the bit decision from the activated sense amplifier equals one, the pre-charged global read line thereby staying pre-charged if the bit decision from the activated sense amplifier equals zero.

Abstract translation: 提供了一种通过包括全局读取行来实践全局读取行共享的存储器，该存储器适于在读取操作之前对全局读取行预充电; 一个接收全局读取线的I / O电路; 以及多个读出放大器，每个读出放大器相对于全局读取行被多路复用，使得在读取操作期间只有多个读出放大器中的所选择的一个读出放大器被激活以确定位决定，该存储器适于放电 如果来自激活的读出放大器的位决定等于1，则预充电的全局读取线等于1，如果来自激活的读出放大器的位决定等于零，则预充电全局读取线由此保持预充电。

公开(公告)号：US20090189685A1

公开(公告)日：2009-07-30

申请号：US12326086

申请日：2008-12-01

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G05F1/10

CPC classification number: H03K19/0016

Abstract: In one embodiment, a leakage reduction circuit is provided that includes: a virtual power supply node; a first PMOS transistor coupled between the virtual power supply node and a power supply node; a second PMOS transistor having a source coupled to the power supply node; and a native NMOS transistor coupled between a drain of the second PMOS transistor and the virtual power supply node, the native NMOS transistor having a gate driven by the power supply node.

Abstract translation: 在一个实施例中，提供了一种泄漏减小电路，其包括：虚拟电源节点; 耦合在虚拟电源节点和电源节点之间的第一PMOS晶体管; 第二PMOS晶体管，其具有耦合到所述电源节点的源极; 以及耦合在所述第二PMOS晶体管的漏极和所述虚拟电源节点之间的天然NMOS晶体管，所述天然NMOS晶体管具有由所述电源节点驱动的栅极。

公开(公告)号：US07567482B2

公开(公告)日：2009-07-28

申请号：US11616573

申请日：2006-12-27

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Cyrus Afghahi

IPC: G11C11/00

CPC classification number: G11C29/81 ,  G06F13/4086 ,  G11C7/06 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Abstract translation: 本发明涉及一种通过替换这种存储器中的小块来提供分层存储器中的冗余的系统和方法。 本发明通过移位预编码线路或者在本地预解码器块中使用修改的移位预解码器电路来提供这种冗余（即，替代这样的小块）。 在一个实施例中，分层存储器结构包括适于被移出使用的至少一个有源预解码器; 以及至少一个适于被移入使用的冗余预解码器。

公开(公告)号：US20090109789A1

公开(公告)日：2009-04-30

申请号：US12108258

申请日：2008-04-23

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: In one embodiment, a decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes: a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true; a (n+1)th switch coupling the dynamic OR node to ground, the (n+1)th switch being controlled such that it turns on if the dynamic OR node is charged, whereby the pre-charged dynamic OR node discharges if the dynamic OR node remains charged; an odd plurality of inverters coupled in series with the dynamic OR node; and a word line driven by the odd plurality of inverters.

Abstract translation: 在一个实施例中，提供一种解码器，用于解码具有从第一地址位a1到最后地址位aN的多个位的地址，每个地址位是真或假，其包括：预充电电路，其适于预先 充电动态NOR节点和动态OR节点，然后允许预充电动态NOR节点和预充电动态OR节点浮动; 耦合在动态NOR节点和地之间的多个开关，每个开关唯一地对应于地址位，使得开关的范围从对应于a1的第一开关到对应于aN的第n个开关，其中对应于真地址位 被配置为仅当其对应的地址位为假时才导通，并且其中对应于假地址位的任何开关被配置为仅在其对应的地址位为真时才导通; 第（n + 1）个开关将动态OR节点耦合到地，第（n + 1）个开关被控制，使得如果动态OR节点被充电，其导通，由此如果 动态OR节点保持充电; 与动态OR节点串联耦合的奇数个反相器; 以及由奇数个反相器驱动的字线。

公开(公告)号：US20090109772A1

公开(公告)日：2009-04-30

申请号：US12031504

申请日：2008-02-14

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba ,  Gregory Long

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba ,  Gregory Long

IPC: G11C8/18 ,  G11C7/00

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: In one embodiment, a random access memory (RAM) is provided that includes: an array of memory cells arranged in rows corresponding to word lines, the memory cells also being arranged in columns corresponding to bit lines; a local clock source that asserts a local clock in response to an assertion of an external clock; a plurality of x-decoders, each x-decoder adapted to assert a corresponding one of the word lines in response to a decoding of an appropriate address, wherein the assertion of a word line couples a corresponding row of the memory cells to their bit lines such that the bit lines are developed with corresponding voltages; and a plurality of sense amplifiers adapted to sense the voltage developments of the bit lines so as to determine a binary content of the memory cells, wherein the local clock source is triggered to de-assert the local clock independently of whether the external clock has been de-asserted.

Abstract translation: 在一个实施例中，提供了一种随机存取存储器（RAM），其包括：排列成与字线对应的行的存储器单元的阵列，所述存储单元也被布置在与位线对应的列中; 响应于外部时钟的断言断言本地时钟的本地时钟源; 多个x解码器，每个x解码器适于响应于适当地址的解码来断言对应的一条字线，其中字线的断言将存储器单元的对应行与其位线相连 使得位线用相应的电压显影; 以及多个感测放大器，其适于感测位线的电压发展，以便确定存储器单元的二进制内容，其中本地时钟源被触发以解除本地时钟的独立于外部时钟是否已被 取消断言。

公开(公告)号：US07519862B2

公开(公告)日：2009-04-14

申请号：US10269201

申请日：2002-10-11

Applicant: Zeynep M. Toros ,  Esin Terzioglu ,  Gil Winograd

Inventor： Zeynep M. Toros ,  Esin Terzioglu ,  Gil Winograd

IPC: G06F11/00

CPC classification number: G06F11/27 ,  G01R31/31705 ,  G01R31/318555 ,  G11C5/04 ,  G11C29/16 ,  G11C2029/0401

Abstract: Aspects of the invention for testing and debugging an embedded device under test may include the step of loading an instruction into a parameterized shift register of a BIST module coupled to each one of a plurality of embedded memory modules comprising the embedded device under test. An identity of the loaded instruction may be determined subsequent to loading the instruction into the parameterized shift register. A plurality of test signals may be generated which correspond to the determined identity of the loaded instruction. In this regard, each of the generated plurality of test signals may control the execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules that make up the embedded device under test.

Abstract translation: 用于测试和调试被测嵌入式设备的本发明的方面可以包括将指令加载到耦合到包括被测嵌入式设备的多个嵌入式存储器模块中的每一个的BIST模块的参数化移位寄存器中的步骤。 可以在将指令加载到参数化移位寄存器之后确定加载指令的身份。 可以生成与确定的加载指令的标识对应的多个测试信号。 在这点上，所生成的多个测试信号中的每个测试信号可以控制组成待测嵌入式设备的多个嵌入式存储器模块中的每一个的对应的一个测试和调试的执行。

公开(公告)号：US20080291728A1

公开(公告)日：2008-11-27

申请号：US12109331

申请日：2008-04-24

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Morteza Cyrus Afghahi

IPC: G11C16/06 ,  H01L29/788 ,  H01L29/94

CPC classification number: G11C16/0425 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

Abstract: A non-volatile memory cell is provided that includes: a substrate including diffusion regions for a read-out transistor; a capacitor formed in a poly-silicon layer adjacent the substrate, the capacitor including a floating gate for the read-out transistor and a control gate, the floating gate and the control gate each having finger extensions, the finger extensions from the floating gate interdigitating with the finger extensions from the control gate; and a programming line coupled to the control gate.

Abstract translation: 提供了一种非易失性存储单元，其包括：包括用于读出晶体管的扩散区域的衬底; 形成在与衬底相邻的多晶硅层中的电容器，所述电容器包括用于读出晶体管的浮置栅极和控制栅极，所述浮置栅极和控制栅极各自具有指状延伸，所述浮动栅极的指状延伸部交叉 手指从控制门延伸; 以及耦合到控制门的编程线。

公开(公告)号：US07411846B2

公开(公告)日：2008-08-12

申请号：US11669400

申请日：2007-01-31

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: G11C7/00

CPC classification number: G11C29/848 ,  G11C5/04 ,  G11C7/06

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can include selectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract translation: 在具有分配给表示存储器结构的逻辑部分的指定的存储单元组的存储器模块中，具有冗余组存储器单元的存储器冗余电路; 以及与指定组和冗余组耦合的冗余控制器。 可以包括冗余解码器的冗余控制器响应于预先选择的存储器组条件（例如，“FAILED”存储器组条件）将冗余组分配给存储器结构的逻辑部分。 冗余控制器还可以包括可选择的开关，例如，可以对预先选择的存储器组条件进行编码的熔丝。 指定组的存储器单元和冗余组的存储器单元可以是存储器行，存储器列，存储器模块的预选部分，存储器模块的可选择部分，存储器模块或其组合。

公开(公告)号：US20080130391A1

公开(公告)日：2008-06-05

申请号：US12016602

申请日：2008-01-18

Applicant: Esin Terzioglu ,  Gil L. Winograd ,  Morteza Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil L. Winograd ,  Morteza Cyrus Afghahi

IPC: G11C7/02

CPC classification number: G11C11/4091 ,  G11C7/02 ,  G11C7/065 ,  G11C7/12 ,  G11C11/401 ,  G11C11/4094 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/2254 ,  H01L27/0207 ,  H01L27/10873 ,  H03K3/356034

Abstract: In one embodiment, a memory is provided that includes: a plurality of memory cells arranged in columns, each column coupled to a corresponding bit line; a sense amplifier adapted to sense the voltage on a pair of the bit lines to determine a binary state of an accessed memory cell coupled to a first one of the bit lines in the pair; and a first trim capacitor having a first terminal directly coupled to one of the bit lines in the pair, the first trim capacitor having an opposing second terminal coupled to a first trim capacitor signal, the memory being adapted to change a voltage of the first trim capacitor signal while the sense amplifier senses the voltage to determine the binary state of the accessed memory cell.

Abstract translation: 在一个实施例中，提供了一种存储器，其包括：以列形式布置的多个存储器单元，每列耦合到对应的位线; 感测放大器，其适于感测一对位线上的电压，以确定耦合到所述对中的所述位线中的第一位的所访问的存储器单元的二进制状态; 以及第一微调电容器，其具有直接耦合到所述一对位线之一的第一端子，所述第一微调电容器具有耦合到第一微调电容器信号的相对的第二端子，所述存储器适于改变所述第一微调电压 电容器信号，而感测放大器感测电压以确定所访问的存储器单元的二进制状态。

公开(公告)号：US07333043B2

公开(公告)日：2008-02-19

申请号：US11203285

申请日：2005-08-15

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: H03M1/12

CPC classification number: H04N5/243 ,  H04N5/23245 ,  H04N5/235

Abstract: An imaging device includes a plurality of photo-diodes arranged in a plurality of columns on a single Complementary Metal Oxide Semiconductor (CMOS) substrate. A plurality of analog-to-digital converters (ADCs) corresponding to the plurality of columns of photo-diodes are arranged on the substrate, with each ADC having an input coupled to outputs of the photo-diodes in the corresponding column. Parallel processing of the data streams produced by the multiple ADCs improves the bandwidth of the imaging device. The ADCs have one or more capacitors based on a reference capacitor that are configured so that the corresponding capacitors for different ADCs are substantially equal across the CMOS substrate. As such, image variation and streaking across the columns of photo-diodes is minimized or eliminated. The reference capacitors of the ADCs are above a minimum capacitance value, determined by a maximum variation of the reference capacitors across the substrate.

Abstract translation: 成像装置包括在单个互补金属氧化物半导体（CMOS）基板上以多列布置的多个光电二极管。 对应于多列光电二极管的多个模数转换器（ADC）布置在衬底上，每个ADC具有耦合到相应列中的光电二极管的输出的输入。 由多个ADC产生的数据流的并行处理提高了成像设备的带宽。 ADC具有基于参考电容器的一个或多个电容器，其被配置为使得用于不同ADC的相应电容器在CMOS衬底上基本相等。 因此，光电二极管列的图像变化和条纹被最小化或消除。 ADC的参考电容器高于最小电容值，由基板上的参考电容器的最大变化量决定。