公开(公告)号：US08811109B2

公开(公告)日：2014-08-19

申请号：US13463873

申请日：2012-05-04

Applicant: Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar

Inventor： Esin Terzioglu ,  Changho Jung ,  Shahzad Nazar

IPC: G11C8/00

CPC classification number: G11C8/10

Abstract: Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods are disclosed. In one embodiment, the memory pre-decoder circuit includes a memory pre-decoder configured to pre-decode a memory address input within a memory pre-decode setup path to generate a pre-decoded memory address input. Additionally, a pulse latch is provided in the memory pre-decoder circuit outside of the memory pre-decode setup path. The pulse latch samples the pre-decoded memory address input based on a clock signal and generates a pre-decoded memory address output. As such, the memory pre-decode setup path sets up the pre-decoded memory address input prior to the clock signal for the pulse latch. In this manner, the pulse latch is configured to generate a pre-decoded memory address output without increasing setup times in the memory pre-decode setup path.

Abstract translation: 公开了采用用于减少存储器访问时间的脉冲锁存器的存储器预解码器电路以及相关的系统和方法。 在一个实施例中，存储器预解码器电路包括存储器预解码器，其被配置为对在存储器预解码设置路径内输入的存储器地址进行预解码以生成预解码的存储器地址输入。 此外，在存储器预解码设置路径外部的存储器预解码器电路中提供脉冲锁存器。 脉冲锁存器基于时钟信号对预解码的存储器地址输入进行采样，并产生预解码的存储器地址输出。 因此，存储器预译码设置路径在脉冲锁存器的时钟信号之前建立预先解码的存储器地址输入。 以这种方式，脉冲锁存器被配置为产生预解码的存储器地址输出，而不增加存储器预解码设置路径中的建立时间。

公开(公告)号：US08331126B2

公开(公告)日：2012-12-11

申请号：US12849862

申请日：2010-08-04

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: G11C17/00 ,  G11C11/00 ,  G11C17/18

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations.

Abstract translation: 非易失性存储器（NVM）位单元的读写操作具有不同的最佳参数，从而在NVM位单元的设计过程中产生冲突。 NVM位单元中的单个位线阻止了最佳的读取性能。 通过将读路径和写入路径分割在两个位线之间的NVM位单元中可以提高读取性能。 NVM位单元的读取位线具有低电容，从而提高读取操作速度并降低功耗。 NVM位单元的写位线具有低电阻以处理写操作期间存在的大电流。 NVM位单元的存储元件可以是保险丝，反熔丝，eFUSE或磁性隧道结。 差分感测读取操作可以进一步增强读取性能。

公开(公告)号：US20120235707A1

公开(公告)日：2012-09-20

申请号：US13295780

申请日：2011-11-14

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true.

Abstract translation: 一种解码器，用于解码具有从第一地址位a1到最后地址位aN的多个位的地址，每个地址位为真或假，其包括预充电电路，其适于预充电动态NOR 节点和动态OR节点，然后允许预充电动态NOR节点和预充电动态OR节点浮动; 耦合在动态NOR节点和地之间的多个开关，每个开关唯一地对应于地址位，使得开关的范围从对应于a1的第一开关到对应于aN的第n个开关，其中对应于真地址位 被配置为仅当其对应的地址位为假时才导通，并且其中对应于假地址位的任何开关被配置为仅在其对应的地址位为真时才导通。

公开(公告)号：US08164362B2

公开(公告)日：2012-04-24

申请号：US10795825

申请日：2004-03-08

Applicant: Morteza Cyrus Afghahi ,  Esin Terzioglu

Inventor： Morteza Cyrus Afghahi ,  Esin Terzioglu

IPC: G01R19/00

CPC classification number: G11C7/06

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract translation: 一种读出放大器，具有对放大器输入信号进行采样的采样电路; 存储与输入信号相对应的参考信号的参考节点; 以及定时电路，以预定间隔激活采样电路，并将参考信号接收到参考节点。 读出放大器还可以包括基本上保持参考信号值的泵电容器; 以及与参考节点耦合并被设置成自适应地调节由读出放大器产生的输出信号的增益的增益电路。 读出放大器可以是单端读出放大器。

公开(公告)号：US08149645B2

公开(公告)日：2012-04-03

申请号：US12750155

申请日：2010-03-30

Applicant: Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

Inventor： Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

IPC: G11C8/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for processing the read and write operations in a memory architecture. The system processing the read and write operations includes at least one local memory block and a synchronously controlled global controller coupled to the local memory block and adapted to extend the high portion of a clock pulse. The method for processing the read and write operations includes skewing a clock pulse using at least one word line interfacing with the global controller.

Abstract translation: 本发明涉及用于处理存储器架构中的读写操作的系统和方法。 处理读和写操作的系统包括耦合到本地存储器块并且适于延长时钟脉冲的高部分的至少一个本地存储器块和同步控制的全局控制器。 用于处理读取和写入操作的方法包括使用与全局控制器接口的至少一个字线来扭曲时钟脉冲。

公开(公告)号：US20110141840A1

公开(公告)日：2011-06-16

申请号：US12968261

申请日：2010-12-14

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: A decoder for decoding an address having a plurality of bits ranging from a first address bit a1 to a last address bit aN, each address bit being either true or false is provided that includes a pre-charge circuit adapted to pre-charge a dynamic NOR node and a dynamic OR node and then allow the pre-charged dynamic NOR node and pre-charged dynamic OR node to float; a plurality of switches coupled between the dynamic NOR node and ground, each switch corresponding uniquely to the address bits such that the switches range from a first switch corresponding to a1 to an nth switch corresponding to aN, wherein any switch corresponding to a true address bit is configured to turn on only if its corresponding address bit is false, and wherein any switch corresponding to a false address bit is configured to turn on only if its corresponding address bit is true; a (n+1)th switch coupling the dynamic OR node to ground, the (n+1)th switch being controlled such that it turns on if the dynamic OR node is charged, whereby the pre-charged dynamic OR node discharges if the dynamic OR node remains charged; an odd plurality of inverters coupled in series with the dynamic OR node; and a word line driven by the odd plurality of inverters.

Abstract translation: 一种解码器，用于解码具有从第一地址位a1到最后地址位aN的多个位的地址，每个地址位为真或假，其包括预充电电路，其适于预充电动态NOR 节点和动态OR节点，然后允许预充电动态NOR节点和预充电动态OR节点浮动; 耦合在动态NOR节点和地之间的多个开关，每个开关唯一地对应于地址位，使得开关的范围从对应于a1的第一开关到对应于aN的第n个开关，其中对应于真地址位 被配置为仅当其对应的地址位为假时才导通，并且其中对应于假地址位的任何开关被配置为仅在其对应的地址位为真时才导通; 第（n + 1）个开关将动态OR节点耦合到地，第（n + 1）个开关被控制，使得如果动态OR节点被充电，其导通，由此如果 动态OR节点保持充电; 与动态OR节点串联耦合的奇数个反相器; 以及由奇数个反相器驱动的字线。

公开(公告)号：US07903497B2

公开(公告)日：2011-03-08

申请号：US12258231

申请日：2008-10-24

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Andreas Gotterba

IPC: G11C8/16

CPC classification number: G11C8/10 ,  G11C7/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/18 ,  G11C11/413

Abstract: In one embodiment, a multi-port SRAM is provided that comprises: a single input port and output port 6-T SRAM; and a multi-port control block circuit that includes: a plurality of input registers corresponding to a plurality of input ports to register corresponding input signals; an input multiplexer to select from the input registers to provide a selected input signal to the 6-T SRAM's single input port; a plurality of output registers corresponding to a plurality of output ports to register corresponding output signals; and an output de-multiplexer to select from the output registers to provide an output signal from the 6-T SRAM's single output port to the selected output register.

Abstract translation: 在一个实施例中，提供了多端口SRAM，其包括：单个输入端口和输出端口6-T SRAM; 以及多端口控制块电路，其包括：对应于多个输入端口的多个输入寄存器，用于寄存对应的输入信号; 输入多路复用器，用于从输入寄存器中选择以向6-T SRAM的单个输入端口提供选定的输入信号; 对应于多个输出端口的多个输出寄存器，用于寄存对应的输出信号; 以及输出解复用器，从输出寄存器中选择，以提供从6-T SRAM单输出端口到所选输出寄存器的输出信号。

公开(公告)号：US07821853B2

公开(公告)日：2010-10-26

申请号：US12190394

申请日：2008-08-12

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: G11C7/00

CPC classification number: G11C29/848 ,  G11C5/04 ,  G11C7/06

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can includeselectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract translation: 在具有分配给表示存储器结构的逻辑部分的指定的存储单元组的存储器模块中，具有冗余组存储器单元的存储器冗余电路; 以及与指定组和冗余组耦合的冗余控制器。 可以包括冗余解码器的冗余控制器响应于预先选择的存储器组条件（例如，“FAILED”存储器组条件）将冗余组分配给存储器结构的逻辑部分。 冗余控制器还可以包括可选择的开关，例如，可以对预先选择的存储器组条件进行编码的熔丝。 指定组的存储器单元和冗余组的存储器单元可以是存储器行，存储器列，存储器模块的预选部分，存储器模块的可选择部分，存储器模块或其组合。

公开(公告)号：US07715262B2

公开(公告)日：2010-05-11

申请号：US12163989

申请日：2008-06-27

Applicant: Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil I. Winograd ,  Melinda L. Miller

Inventor： Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil I. Winograd ,  Melinda L. Miller

IPC: G11C7/02

CPC classification number: G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/025 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/1204

Abstract: In one embodiment, a hybrid DRAM is provided that includes: a sense amplifier including a differential amplifier and regenerative latch, wherein the differential amplifier and regenerative latch are constructed using core transistors that have a relatively thin gate oxide; and a plurality of memory cells coupled to the sense amplifier through a pair of bit lines, wherein each memory cell includes an access transistor coupled to a storage cell, the access transistor having a relatively thick gate oxide, whereby the storage capacitor is capable of being charged to a VIO power supply voltage that is greater than a VDD power supply voltage for the core transistors.

Abstract translation: 在一个实施例中，提供了一种混合DRAM，其包括：包括差分放大器和再生锁存器的读出放大器，其中差分放大器和再生锁存器使用具有相对薄的栅极氧化物的核心晶体管构成; 以及多个存储单元，其通过一对位线耦合到读出放大器，其中每个存储单元包括耦合到存储单元的存取晶体管，所述存取晶体管具有相对较厚的栅极氧化物，由此所述存储电容器能够 被充电到大于核心晶体管的VDD电源电压的VIO电源电压。

公开(公告)号：US20090316512A1

公开(公告)日：2009-12-24

申请号：US12491864

申请日：2009-06-25

Applicant: Esin Terzioglu ,  Gil I. Winograd ,  Cyrus Afghahi

Inventor： Esin Terzioglu ,  Gil I. Winograd ,  Cyrus Afghahi

IPC: G11C8/00 ,  G11C8/10 ,  G11C29/00

CPC classification number: G11C29/81 ,  G06F13/4086 ,  G11C7/06 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/808 ,  G11C29/848 ,  Y02D10/14 ,  Y02D10/151

Abstract: The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines or using a modified shifting predecoder circuit in the local predecoder block. In one embodiment, the hierarchal memory structure includes at least one active predecoder adapted to be shifted out of use; and at least one redundant predecoder adapted to be shifted in to use.

Abstract translation: 本发明涉及一种通过替换这种存储器中的小块来提供分层存储器中的冗余的系统和方法。 本发明通过移位预编码线路或者在本地预解码器块中使用修改的移位预解码器电路来提供这种冗余（即，替代这样的小块）。 在一个实施例中，分层存储器结构包括适于被移出使用的至少一个有源预解码器; 以及至少一个适于被移入使用的冗余预解码器。