公开(公告)号：US20080026512A1

公开(公告)日：2008-01-31

申请号：US11867213

申请日：2007-10-04

申请人： RAJIV JOSHI ,  Louis Hsu ,  Oleg Gluschenkov

发明人： RAJIV JOSHI ,  Louis Hsu ,  Oleg Gluschenkov

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/78654

摘要： An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

摘要翻译： 一种集成电路（IC）芯片，其可以是具有绝缘体上硅（SOI）场效应晶体管（FET）和制造芯片的方法的体CMOS IC芯片。 IC芯片包括具有埋入绝缘体层的凹坑的区域，并且在层上形成的FET是SOI FET。 SOI FET可以包括部分耗尽的SOI（PD-SOI）FET和完全耗尽的SOI（FD-SOI）FET，并且芯片也可以包括体FET。 FET通过轮廓化晶片的表面，将氧气保形地均匀地注入到均匀的深度，并平坦化以去除体FET区域中的掩埋氧化物（BOX）来形成。

公开(公告)号：US07312134B2

公开(公告)日：2007-12-25

申请号：US11741441

申请日：2007-04-27

申请人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Omer H. Dokumaci ,  Bruce B. Doris ,  Oleg Gluschenkov ,  Huilong Zhu

IPC分类号： H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：US20070262348A1

公开(公告)日：2007-11-15

申请号：US11782351

申请日：2007-07-24

申请人： Dae-Gyu Park ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Kwong Wong

发明人： Dae-Gyu Park ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Kwong Wong

IPC分类号： H01L21/3205 ,  H01L29/73

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.

摘要翻译： 本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。

公开(公告)号：US20060289909A1

公开(公告)日：2006-12-28

申请号：US11514605

申请日：2006-09-01

申请人： Oleg Gluschenkov ,  Jack Mandelman ,  Michael Belyansky ,  Bruce Doris

发明人： Oleg Gluschenkov ,  Jack Mandelman ,  Michael Belyansky ,  Bruce Doris

IPC分类号： H01L29/76

CPC分类号： H01L21/76834 ,  H01L21/28052 ,  H01L21/76897 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A CMOS structure in which the gate-to-drain/source capacitance is reduced as well as various methods of fabricating such a structure are provided. In accordance with the present invention, it has been discovered that the gate-to-drain/source capacitance can be significantly reduced by forming a CMOS structure in which a low-k dielectric material is self-aligned with the gate conductor. A reduction in capacitance between the gate conductor and the contact via ranging from about 30% to greater than 40% has been seen with the inventive structures. Moreover, the total outer-fringe capacitance (gate to outer diffusion+gate to contact via) is reduced between 10-18%. The inventive CMOS structure includes at least one gate region including a gate conductor located a top a surface of a semiconductor substrate; and a low-k dielectric material that is self-aligned to the gate conductor.

摘要翻译： 提供其中栅极 - 漏极/源极电容减小的CMOS结构以及制造这种结构的各种方法。 根据本发明，已经发现，通过形成其中低k电介质材料与栅极导体自对准的CMOS结构，可以显着降低栅 - 漏/源电容。 本发明的结构已经看到，栅极导体和接触孔之间的电容减小范围为约30％至大于40％。 此外，总外部电容（门到外部扩散+接触通孔的栅极）在10-18％之间降低。 本发明的CMOS结构包括至少一个栅极区域，其包括位于半导体衬底的表面顶部的栅极导体; 以及与栅极导体自对准的低k电介质材料。

公开(公告)号：US20060255375A1

公开(公告)日：2006-11-16

申请号：US10908442

申请日：2005-05-12

申请人： Omer Dokumaci ,  Oleg Gluschenkov

发明人： Omer Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L31/112

CPC分类号： H01L29/105 ,  H01L21/26586 ,  H01L21/823412 ,  H01L29/6659 ,  H01L29/66636

摘要： An apparatus and method for controlling the net doping in the active region of a semiconductor device in accordance with a gate length is provided. A compensating dopant is chosen to be a type of dopant which will electrically neutralize dopant of the opposite type in the substrate. By implanting the compensating dopant at relatively high angle and high energy, the compensating dopant will pass into and through the gate region for short channels and have little or no impact on the total dopant concentration within the gate region. Where the channel is of a longer length, the high implant angle and the high implant energy cause the compensating dopant to lodge within the channel thereby neutralizing a portion of the dopant of the opposite type.

摘要翻译： 提供了一种用于根据栅极长度控制半导体器件的有源区域中的净掺杂的装置和方法。 选择补偿掺杂剂是一种掺杂剂，其将电中和衬底中相反类型的掺杂剂。 通过以相对高的角度和高能量注入补偿掺杂剂，补偿掺杂剂将进入并通过用于短通道的栅极区域，并且对栅极区域内的总掺杂剂浓度几乎没有或没有影响。 在通道长度较长的情况下，高注入角度和高注入能量使得补偿掺杂剂落入通道内，从而中和相反类型的掺杂剂的一部分。

公开(公告)号：US20060237803A1

公开(公告)日：2006-10-26

申请号：US10907935

申请日：2005-04-21

申请人： Wenjuan Zhu ,  Michael Chudzik ,  Oleg Gluschenkov ,  Dae-Gyu Park ,  Akihisa Sekiguchi

发明人： Wenjuan Zhu ,  Michael Chudzik ,  Oleg Gluschenkov ,  Dae-Gyu Park ,  Akihisa Sekiguchi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/28185 ,  H01L21/28097 ,  H01L21/28229 ,  H01L21/823857 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

摘要： A semiconductor structure and method of forming the same, comprising forming a uniform buffer layer of diffusion-controlling stable material on top of a base gate dielectric layer, and then forming a uniform layer which contains a source of transitional metal atoms, and then annealing the structure to diffuse the transitional metal atoms from their source through the diffusion-controlling material and into the base gate dielectric layer.

摘要翻译： 一种半导体结构及其制造方法，包括在基极电介质层的顶部形成扩散控制稳定材料的均匀缓冲层，然后形成含有过渡金属原子源的均匀层，然后退火 结构将过渡金属原子从其源极扩散通过扩散控制材料并进入基极栅极电介质层。

公开(公告)号：US20060125008A1

公开(公告)日：2006-06-15

申请号：US10905062

申请日：2004-12-14

申请人： Dureseti Chidambarrao ,  Bruce Doris ,  Oleg Gluschenkov ,  Omer Dokumaci ,  Huilong Zhu

发明人： Dureseti Chidambarrao ,  Bruce Doris ,  Oleg Gluschenkov ,  Omer Dokumaci ,  Huilong Zhu

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L21/84 ,  H01L27/1203 ,  H01L29/7843 ,  Y10S438/938

摘要： The present invention provides a strained-Si structure, in which the nFET regions of the structure are strained in tension and the pFET regions of the structure are strained in compression. Broadly the strained-Si structure comprises a substrate; a first layered stack atop the substrate, the first layered stack comprising a compressive dielectric layer atop the substrate and a first semiconducting layer atop the compressive dielectric layer, wherein the compressive dielectric layer transfers tensile stresses to the first semiconducting layer; and a second layered stack atop the substrate, the second layered stack comprising an tensile dielectric layer atop the substrate and a second semiconducting layer atop the tensile dielectric layer, wherein the tensile dielectric layer transfers compressive stresses to the second semiconducting layer. The tensile dielectric layer and the compressive dielectric layer preferably comprise nitride, such as Si3N4.

摘要翻译： 本发明提供一种应变Si结构，其中该结构的nFET区域被拉紧并且该结构的pFET区域被压缩而变形。 广义上，应变Si结构包括基底; 所述第一层叠堆叠包括位于所述衬底顶部的压缩介电层和位于所述压缩介电层顶部的第一半导体层，其中所述压缩介电层将拉伸应力传递到所述第一半导体层; 以及在所述衬底顶部的第二层叠堆叠，所述第二层叠堆叠包括位于所述衬底顶部的拉伸介电层和位于所述拉伸介电层顶部的第二半导体层，其中所述拉伸介电层将压缩应力传递到所述第二半导体层。 拉伸介电层和压电介电层优选包括氮化物，例如Si 3 N 4 N 4。

公开(公告)号：US20060118825A1

公开(公告)日：2006-06-08

申请号：US11337398

申请日：2006-01-23

申请人： Omer Dokumaci ,  Oleg Gluschenkov

发明人： Omer Dokumaci ,  Oleg Gluschenkov

IPC分类号： H01L29/06

CPC分类号： H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/82385 ,  Y10S438/947

摘要： A self-correcting etching (SCORE) process for fabricating microstructure is provided. The SCORE process of the present invention is particularly useful for reducing preselected features of a hard mask without degrading the variation of the critical dimension (CD) within each wafer. Alternatively; the CD variation of the hard mask features' produced during printing can be substantially reduced by applying SCORE. Hence, ultra-sub-lithographic features (e.g., nanostructures) can be reliably fabricated. Consequently, the method of the present invention can be used to increase the circuit performance, while improving the manufacturing yield.

摘要翻译： 提供了用于制造微结构的自校正蚀刻（SCORE）工艺。 本发明的SCORE方法对于降低硬掩模的预选特征而不降低每个晶片内的临界尺寸（CD）的变化特别有用。 或者; 通过应用SCORE可以显着降低印刷过程中产生的硬掩模特征的CD变化。 因此，可以可靠地制造超亚光刻特征（例如，纳米结构）。 因此，本发明的方法可以用于提高电路性能，同时提高制造成品率。

公开(公告)号：US20060060925A1

公开(公告)日：2006-03-23

申请号：US10711416

申请日：2004-09-17

申请人： Bruce Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

发明人： Bruce Doris ,  Oleg Gluschenkov ,  MeiKei Ieong ,  Effendi Leobandung ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L29/045 ,  H01L21/76275 ,  H01L21/76278 ,  H01L21/823807 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7842

摘要： Semiconductor structure and method to simultaneously achieve optimal stress type and current flow for both nFET and pFET devices, and for gates orientated in one direction, are disclosed. One embodiment of the method includes bonding a first wafer having a first surface direction and a first surface orientation atop a second wafer having a different second surface orientation and a different second surface direction; forming an opening through the first wafer to the second wafer; and forming a region in the opening coplanar with a surface of the first wafer, wherein the region has the second surface orientation and the second surface direction. The semiconductor device structure includes at least two active regions having different surface directions, each active region including one of a plurality of nFETs and a plurality of pFETs, and wherein a gate electrode orientation is such that the nFETs and the pFETs are substantially parallel to each other.

摘要翻译： 公开了同时实现nFET和pFET器件以及朝向一个方向的栅极的最佳应力类型和电流流动的半导体结构和方法。 该方法的一个实施例包括将具有第一表面方向的第一晶片和具有不同的第二表面取向和不同的第二表面方向的第二晶片顶部的第一表面取向接合; 形成通过所述第一晶片的开口到所述第二晶片; 以及在所述开口中形成与所述第一晶片的表面共面的区域，其中所述区域具有第二表面取向和所述第二表面方向。 半导体器件结构包括具有不同表面方向的至少两个有源区，每个有源区包括多个nFET和多个pFET中的一个，并且其中栅电极取向使得nFET和pFET基本上平行于每个 其他。

公开(公告)号：US20060043421A1

公开(公告)日：2006-03-02

申请号：US10711200

申请日：2004-09-01

申请人： Bruce Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

发明人： Bruce Doris ,  Oleg Gluschenkov ,  Ying Zhang ,  Huilong Zhu

IPC分类号： H01L27/10

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A multi-gate device has a high-k dielectric layer for a top channel of the gate and a protective layer for use in a finFET device. The high-k dielectric layer is placed on the top surface of the channel of the finFET and may reduce or eliminate silicon consumption in the channel. The use of the high-k dielectric layer on the top surface reduces hysteresis and mobility degradation associated with high-k dielectrics. The protection layer may protect the high-k dielectric layer during an etching process.

摘要翻译： 多栅极器件具有用于栅极顶部沟道的高k电介质层和用于finFET器件的保护层。 高k电介质层被放置在finFET的沟道的顶表面上，并且可以减少或消除沟道中的硅消耗。 在顶表面上使用高k电介质层减少了与高k电介质相关的滞后和迁移率降低。 保护层可以在蚀刻过程中保护高k电介质层。