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    Application of cluster beam implantation for fabricating threshold voltage adjusted FETs
    3.
    发明授权
    Application of cluster beam implantation for fabricating threshold voltage adjusted FETs 有权
    应用聚束束注入制造阈值电压调节FET

    公开(公告)号：US08288222B2

    公开(公告)日：2012-10-16

    申请号：US12582139

    申请日：2009-10-20

    申请人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

    发明人： Oleg Gluschenkov ,  Dae-Gyu Park ,  Haizhou Yin

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857

    摘要： Semiconductor structures including a high k gate dielectric material that has at least one surface threshold voltage adjusting region located within 3 nm or less from an upper surface of the high k gate dielectric are provided. The at least one surface threshold voltage adjusting region is formed by a cluster beam implant step in which at least one threshold voltage adjusting impurity is formed directly within the high k gate dielectric or driven in from an overlying threshold voltage adjusting material which is subsequently removed from the structure following the cluster beam implant step.

    摘要翻译： 提供了包括高k栅介质材料的半导体结构，其具有位于距离高k栅极电介质的上表面3nm以内的至少一个表面阈值电压调整区域。 所述至少一个表面阈值电压调整区域通过聚束射束注入步骤形成，其中至少一个阈值电压调节杂质直接形成在所述高k栅极电介质内或从上限的阈值电压调节材料驱动，所述材料随后从 聚束束植入步骤后的结构。

    STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR
    4.
    发明申请
    STRUCTURE OF HIGH-K METAL GATE SEMICONDUCTOR TRANSISTOR 有权
    高K金属栅极半导体晶体管的结构

    公开(公告)号：US20120098067A1

    公开(公告)日：2012-04-26

    申请号：US12908024

    申请日：2010-10-20

    申请人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

    发明人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

    IPC分类号： H01L27/092 ,  H01L27/12

    CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

    摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.

    摘要翻译： 提供半导体结构。 该结构包括直接在应变硅层的顶部形成的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是 通过一层硅 - 锗（SiGe）。 应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。 此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。 还提供了形成半导体结构的方法。

    Temperature stable metal nitride gate electrode
    5.
    发明授权
    Temperature stable metal nitride gate electrode 有权
    温度稳定的金属氮化物栅电极

    公开(公告)号：US07282403B2

    公开(公告)日：2007-10-16

    申请号：US11203952

    申请日：2005-08-15

    申请人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

    发明人： Dae-Gyu Park ,  Cyril Cabral, Jr. ,  Oleg Gluschenkov ,  Hyungjun Kim

    IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/4763

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

    摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

    摘要翻译： 提供了一种集成电路，其包括形成在衬底上的FET栅极结构。 该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。 该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。 优选地，该层为W N x X，x为约0.9。 改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。 特别地，在WN 层中改变x允许调节不同FET中的阈值电压。 多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

    METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS
    6.
    发明申请
    METHOD OF PRODUCING BONDED WAFER STRUCTURE WITH BURIED OXIDE/NITRIDE LAYERS 审中-公开
    用氧化铝/氮化物层生产粘结的结构的方法

    公开(公告)号：US20110180896A1

    公开(公告)日：2011-07-28

    申请号：US12692983

    申请日：2010-01-25

    申请人： Gerd Pfeiffer ,  Haizhou Yin ,  Edmund J. Sprogis ,  Subramanian Iyer ,  Zhibin Ren ,  Dae-Gyu Park ,  Oleg Gluschenkov

    发明人： Gerd Pfeiffer ,  Haizhou Yin ,  Edmund J. Sprogis ,  Subramanian Iyer ,  Zhibin Ren ,  Dae-Gyu Park ,  Oleg Gluschenkov

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L21/76256

    摘要： A method of forming a bonded wafer structure includes providing a first semiconductor wafer substrate having a first silicon oxide layer at the top surface of the first semiconductor wafer substrate; providing a second semiconductor wafer substrate; forming a second silicon oxide layer on the second semiconductor wafer substrate; forming a silicon nitride layer on the second silicon oxide layer; and bringing the first silicon oxide layer of the first semiconductor wafer substrate into physical contact with the silicon nitride layer of the second semiconductor wafer substrate to form a bonded interface between the first silicon oxide layer and the silicon nitride layer. Alternatively, a third silicon oxide layer may be formed on the silicon nitride layer before bonding. A bonded interface is then formed between the first and third silicon oxide layers. A bonded wafer structure formed by such a method is also provided.

    摘要翻译： 形成接合晶片结构的方法包括：在第一半导体晶片衬底的顶表面上提供具有第一氧化硅层的第一半导体晶片衬底; 提供第二半导体晶片衬底; 在所述第二半导体晶片衬底上形成第二氧化硅层; 在所述第二氧化硅层上形成氮化硅层; 并且使第一半导体晶片衬底的第一氧化硅层与第二半导体晶片衬底的氮化硅层物理接触以在第一氧化硅层和氮化硅层之间形成键合界面。 或者，可以在接合之前在氮化硅层上形成第三氧化硅层。 然后在第一和第三氧化硅层之间形成键合界面。 还提供了通过这种方法形成的接合晶片结构。

    Temperature stable metal nitride gate electrode
    7.
    发明申请
    Temperature stable metal nitride gate electrode 有权

    公开(公告)号：US20060040439A1

    公开(公告)日：2006-02-23

    申请号：US11203952

    申请日：2005-08-15

    申请人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

    发明人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

    摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

    High-temperature stable gate structure with metallic electrode
    8.
    发明申请
    High-temperature stable gate structure with metallic electrode 有权
    具有金属电极的高温稳定栅极结构

    公开(公告)号：US20050282341A1

    公开(公告)日：2005-12-22

    申请号：US10869658

    申请日：2004-06-16

    申请人： Dae-Gyu Park ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Kwong Wong

    发明人： Dae-Gyu Park ,  Oleg Gluschenkov ,  Michael Gribelyuk ,  Kwong Wong

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/44 ,  H01L29/49 ,  H01L29/51

    CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28229 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    摘要： The present invention provides a method for depositing a dielectric stack comprising forming a dielectric layer atop a substrate, the dielectric layer comprising at least oxygen and silicon atoms; forming a layer of metal atoms atop the dielectric layer within a non-oxidizing atmosphere, wherein the layer of metal atoms has a thickness of less than about 15 Å; forming an oxygen diffusion barrier atop the layer of metal atoms, wherein the non-oxidizing atmosphere is maintained; forming a gate conductor atop the oxygen diffusion barrier; and annealing the layer of metal atoms and the dielectric layer, wherein the layer of metal atoms reacts with the dielectric layer to provide a continuous metal oxide layer having a dielectric constant ranging from about 25 to about 30 and a thickness less than about 15 Å.

    摘要翻译： 本发明提供一种用于沉积电介质堆叠的方法，包括在衬底顶部形成电介质层，所述电介质层至少包含氧和硅原子; 在非氧化性气氛中在所述电介质层的顶部形成金属原子层，其中所述金属原子层具有小于约的厚度; 在金属原子层的上方形成氧扩散阻挡层，其中保持非氧化性气氛; 在氧扩散阻挡层上形成栅极导体; 以及退火所述金属原子层和所述介电层，其中所述金属原子层与所述电介质层反应以提供介电常数范围为约25至约30且厚度小于约的连续金属氧化物层。

    Structure of high-K metal gate semiconductor transistor
    9.
    发明授权
    Structure of high-K metal gate semiconductor transistor 有权
    高K金属栅半导体晶体管的结构

    公开(公告)号：US08643061B2

    公开(公告)日：2014-02-04

    申请号：US12908024

    申请日：2010-10-20

    申请人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

    发明人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

    IPC分类号： H01L29/66

    CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

    摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.

    摘要翻译： 提供半导体结构。 该结构包括直接形成在应变硅层的顶部上的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是 通过一层硅 - 锗（SiGe）。 应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。 此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。 还提供了形成半导体结构的方法。