公开(公告)号：US07392033B2

公开(公告)日：2008-06-24

申请号：US11084930

申请日：2005-03-21

Applicant: Hooman Darabi

Inventor： Hooman Darabi

IPC: H04B1/26

CPC classification number: H03F1/26 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/1483 ,  H03D2200/0043 ,  H03D2200/0084 ,  H03F3/45183 ,  H03F2200/294 ,  H03F2200/372 ,  H03F2203/45362

Abstract: A mixer is disclosed that includes first and second transconductance modules that, in one embodiment, includes MOSFETs configured to receive a plurality of signals that are to be mixed and a selectively coupled auxiliary current source to inject an auxiliary current into the second transconductance module approximately at or near a zero-crossing point in order to reduce flicker noise and other noise introduced into an output signal during switching. Accordingly, as a first transconductance module approaches a zero-crossing, auxiliary current is injected to reduce the current produced therefrom thereby reducing flicker noise. In a differential mixer, the amount of current produced from a transistor pair to which the signal cycle is being switched is also reduced thereby reducing noise from the transistor pair that is turning on for the next portion of a signal cycle.

Abstract translation: 公开了一种混合器，其包括第一和第二跨导模块，其在一个实施例中包括被配置为接收要混合的多个信号的MOSFET，以及选择性耦合的辅助电流源，用于将辅助电流注入到第二跨导模块中 或靠近零交叉点，以便在切换期间减少引入到输出信号中的闪烁噪声和其它噪声。 因此，当第一跨导模块接近零交叉时，辅助电流被注入以减少由此产生的电流从而降低闪烁噪声。 在差分混频器中，从信号周期切换到的晶体管对产生的电流量也减小，从而降低了在信号周期的下一部分导通的晶体管对的噪声。

公开(公告)号：US20080146170A1

公开(公告)日：2008-06-19

申请号：US11638622

申请日：2006-12-13

Applicant: Mohammad Nariman ,  Alireza Zolfaghari ,  Hooman Darabi

Inventor： Mohammad Nariman ,  Alireza Zolfaghari ,  Hooman Darabi

IPC: H04B1/02 ,  H03M1/66

CPC classification number: H04B1/0483

Abstract: A digital to analog conversion (DAC) module includes a digital to analog converter, a sample and hold circuit, and a switch module. The digital to analog converter is coupled to convert a digital signal into an analog signal. The sample and hold circuit is coupled to sample the analog signal to produce a sampled analog signal. The switch module is coupled to provide the analog signal as an output of the DAC module when the DAC module in a first mode and to output the analog signal to the sample and hold circuit when the DAC module in a second mode, wherein the sampled analog signal provides the output of the DAC module in the second mode.

Abstract translation: 数模转换（DAC）模块包括数模转换器，采样保持电路和开关模块。 数模转换器被耦合以将数字信号转换为模拟信号。 采样和保持电路被耦合以对模拟信号进行采样以产生采样的模拟信号。 当DAC模块处于第一模式时，开关模块被耦合以提供作为DAC模块的输出的模拟信号，并且当DAC模块处于第二模式时，将模拟信号输出到采样和保持电路，其中， 采样模拟信号在第二模式下提供DAC模块的输出。

公开(公告)号：US07356325B2

公开(公告)日：2008-04-08

申请号：US11173043

申请日：2005-07-01

Applicant: Arya Reza Behzad ,  Hooman Darabi

Inventor： Arya Reza Behzad ,  Hooman Darabi

IPC: H04B1/26 ,  H04B1/28 ,  H04M1/00

CPC classification number: H04B1/0082

Abstract: Local oscillation circuitry for use in an RF transceiver Integrated Circuit (IC) includes local oscillation generation circuitry operable to produce a local oscillation and local oscillation distribution circuitry. The local oscillation distribution circuitry includes a splitting circuit, a first distribution portion, and a second distribution portion. The splitting circuit receives the local oscillation and produces multiple copies of the local oscillation. The first distribution portion produces a first local oscillation corresponding to a first RF band and a second local oscillation corresponding to a second RF band based and to provide the first local oscillation and the second local oscillation to a first RF transceiver group. The second distribution portion produces a first local oscillation and a second local oscillation and provides the first local oscillation and the second local oscillation to the second RF transceiver group.

Abstract translation: 用于RF收发器的本地振荡电路集成电路（IC）包括可操作以产生本地振荡和本地振荡分配电路的本地振荡发生电路。 本地振荡分配电路包括分离电路，第一分配部分和第二分配部分。 分离电路接收本地振荡并产生本地振荡的多个副本。 第一分配部分产生对应于第一RF频带的第一本地振荡和对应于第二RF频带的第二本地振荡，并且向第一RF收发机组提供第一本地振荡和第二本地振荡。 第二分配部分产生第一本地振荡和第二本地振荡，并将第一本地振荡和第二本地振荡提供给第二RF收发器组。

公开(公告)号：US20070165708A1

公开(公告)日：2007-07-19

申请号：US11333729

申请日：2006-01-17

Applicant: Hooman Darabi ,  Henrik Jensen ,  Alireza Zolfaghari

Inventor： Hooman Darabi ,  Henrik Jensen ,  Alireza Zolfaghari

IPC: H04B1/38 ,  H04L27/04 ,  H04L27/12

CPC classification number: H04L27/364 ,  H03C3/0925 ,  H03C3/0933 ,  H03F3/24 ,  H03F2200/331 ,  H03L7/1976 ,  H04L27/361

Abstract: Various embodiments are disclosed relating to wireless systems, and relating to wireless transceivers. In an example embodiment, the wireless transceiver may include a voltage controlled oscillator (VCO) that may be controlled by a phase-locked loop (PLL). A fractional-N divider may be coupled to a feedback loop of the PLL and a delta-sigma modulator may control the fractional-N divider to vary the divider number of the fractional-N divider to cause the VCO to output a modulated frequency spectrum. In another embodiment, modulation path calibration may be performed by inputting an amplitude and phase modulated transmit spectrum to the transceiver's receiver to be demodulated. The demodulated transmit spectrum may then be analyzed to determine if the transmit spectrum meets one or more signal requirements, such as falling within a required spectral mask. The AM path delay and/or the PM path delay of the transmitter may be adjusted to decrease a mismatch in timing or delay between the AM and PM paths.

Abstract translation: 公开了与无线系统有关并涉及无线收发器的各种实施例。 在示例实施例中，无线收发器可以包括可由锁相环（PLL）控制的压控振荡器（VCO）。 分数N分频器可以耦合到PLL的反馈环路，并且Δ-Σ调制器可以控制分数N分频器来改变分数N分频器的分频器数，以使VCO输出调制的频谱。 在另一个实施例中，调制路径校准可以通过将幅度和相位调制的发送频谱输入到收发器的接收机进行解调。 然后可以分析解调的发射频谱，以确定发射频谱是否满足一个或多个信号要求，例如落入所需频谱掩模内。 可以调整发射机的AM路径延迟和/或PM路径延迟以减少AM和PM路径之间的定时或延迟的不匹配。

公开(公告)号：US20070092038A1

公开(公告)日：2007-04-26

申请号：US11260848

申请日：2005-10-26

Applicant: Qiang Li ,  Hooman Darabi

Inventor： Qiang Li ,  Hooman Darabi

IPC: H03D3/00

CPC classification number: H03H11/1291

Abstract: Configuring a multiple stage band pass filter of a radio frequency receiver commences by setting a comer of a low pass mixer output filter that receives a down sampled analog information signal. Operation continues with setting a buffer output filter comer of a low pass buffer output filter coupled to an output of low pass mixer output filter via a buffer. Then, operation includes setting the poles and zero of a plurality of band pass filters coupled to the output of the low pass buffer output filter is performed. This operation includes first setting a zero of a respected band pass filter and then setting the plurality of poles of the band pass filter. Finally, operation concludes with setting a combined gain of the combination of the low pass mixer output filter, the low pass buffer output filter, and the plurality of band pass filters.

Abstract translation: 通过设置接收下采样模拟信号信号的低通混频器输出滤波器的角，开始配置射频接收机的多级带通滤波器。 通过缓冲器将低通缓冲器输出滤波器的缓冲器输出滤波器设置为低通混频器输出滤波器的输出，继续进行操作。 然后，操作包括设置耦合到低通缓冲器输出滤波器的输出的多个带通滤波器的极点和零点。 该操作包括首先设置带宽滤波器的零值，然后设置带通滤波器的多个极点。 最后，通过设置低通混频器输出滤波器，低通缓冲器输出滤波器和多个带通滤波器的组合的组合增益来进行操作。

公开(公告)号：US07196582B2

公开(公告)日：2007-03-27

申请号：US10977798

申请日：2004-10-29

Applicant: Hooman Darabi ,  Janice Chiu

Inventor： Hooman Darabi ,  Janice Chiu

IPC: H03G3/10

CPC classification number: H03G1/007 ,  H03G3/3063 ,  H03G2201/103 ,  H03G2201/202 ,  H03G2201/307

Abstract: Methods and systems for processing signals are disclosed herein. In one aspect of the invention a circuit for processing signals may comprise a triple well (TW) NMOS transistor coupled to an amplifier core. The TW NMOS transistor may track process and temperature variations (PVT) of at least one NMOS transistor within the amplifier core. A drain of the TW NMOS transistor may be coupled to a first inductor and the first inductor may be coupled to a first voltage source. The first voltage source may generate a standard voltage of about 1.2V. A source of the TW NMOS transistor may be coupled to a second inductor and the second inductor may be coupled to the first voltage source. A gate of the TW NMOS transistor may be coupled to a second voltage source, where the second voltage source may generate a standard voltage of about 2.5V.

Abstract translation: 本文公开了用于处理信号的方法和系统。 在本发明的一个方面，用于处理信号的电路可以包括耦合到放大器芯的三阱（TW）NMOS晶体管。 TW NMOS晶体管可跟踪放大器核心内的至少一个NMOS晶体管的工艺和温度变化（PVT）。 TW NMOS晶体管的漏极可以耦合到第一电感器，并且第一电感器可以耦合到第一电压源。 第一电压源可产生约1.2V的标准电压。 TW NMOS晶体管的源极可以耦合到第二电感器，并且第二电感器可以耦合到第一电压源。 TW NMOS晶体管的栅极可以耦合到第二电压源，其中第二电压源可以产生约2.5V的标准电压。

公开(公告)号：US20070032216A1

公开(公告)日：2007-02-08

申请号：US11544343

申请日：2006-10-06

Applicant: Hooman Darabi

Inventor： Hooman Darabi

IPC: H04B1/28

CPC classification number: H03F1/223 ,  H03F3/72 ,  H03F2200/294 ,  H03F2200/453 ,  H03F2203/7233 ,  H03G1/0088 ,  H03G3/3052 ,  H04B1/18 ,  H04B1/406

Abstract: A circuit is formed to steer current in and out of an inductive load in a manner that enables an amplifier to provide a plurality of gain steps without modifying an LC time constant for the circuit and, therefore, without modifying the tuning or frequency of oscillation for the circuit. A first group of MOSFETs are coupled in parallel and define the circuit current flow. A second group of MOSFETs are coupled in parallel to each other and in series to an impedance device. A third group of MOSFETs coupled to steer current in and out of the impedance device to affect the output signal coupled to one end of the impedance device. The transistors in the second and third groups of MOSFETs are selectively activated to control the amount of current that goes through the impedance device.

Abstract translation: 电路形成为以电流负载的方式引导电流，使得放大器能够提供多个增益步骤而不修改电路的LC时间常数，因此不改变振荡的调谐或振荡频率 电路。 第一组MOSFET并联并定义电路电流。 第二组MOSFET彼此并联并串联耦合到阻抗器件。 第三组MOSFET，其耦合以引导进入和流出阻抗器件的电流，以影响耦合到阻抗器件的一端的输出信号。 选择性地激活第二组和第三组MOSFET中的晶体管以控制通过阻抗器件的电流量。

公开(公告)号：US20060094386A1

公开(公告)日：2006-05-04

申请号：US10976976

申请日：2004-10-29

Applicant: Hooman Darabi ,  Brima Ibrahim ,  Hea Kim

Inventor： Hooman Darabi ,  Brima Ibrahim ,  Hea Kim

IPC: H04B1/00 ,  H04B1/10

CPC classification number: H04L25/061 ,  H03D3/008 ,  H04B1/30 ,  H04L25/0272 ,  H04L25/0294 ,  H04L25/0296

Abstract: In RF transceivers, a method and system for a second order input intercept point (IIP2) calibration scheme are provided. Transceiver calibration schemes to compensate for DC offsets produced by interfering signals may be performed during production testing or field operation. During production testing, an external source may inject a blocker signal that produces DC offsets in the receiver portion of the transceiver. A transceiver switch may be set to receive mode in this scheme. During field operation, a power amplifier in the transmitter portion of the transceiver may inject the blocker signal. In this scheme, the switch may be set to transmit mode and the DC offsets are produced by the portion of the injected blocker signal that leaks through the switch. In both schemes, a DC offset sensor detects DC offsets in the I/Q signal paths and may determine compensation currents which may be applied by injection circuits.

Abstract translation: 在RF收发器中，提供了用于二阶输入截点（IIP2）校准方案的方法和系统。 可以在生产测试或现场操作期间执行用于补偿由干扰信号产生的直流偏移的收发器校准方案。 在生产测试期间，外部源可以注入在收发器的接收器部分中产生DC偏移的阻塞信号。 可以在该方案中将收发器开关设置为接收模式。 在场操作期间，收发器的发射器部分中的功率放大器可以注入阻塞信号。 在该方案中，开关可以被设置为发送模式，并且DC偏移由注入的阻塞信号的部分通过开关泄漏产生。 在两种方案中，DC偏移传感器检测I / Q信号路径中的直流偏移，并且可以确定可由注入电路施加的补偿电流。

公开(公告)号：US20060035668A1

公开(公告)日：2006-02-16

申请号：US10922531

申请日：2004-08-20

Applicant: Qiang Li ,  Hooman Darabi

Inventor： Qiang Li ,  Hooman Darabi

IPC: H04B1/38

CPC classification number: H04B1/0071

Abstract: A dual-band input transceiver block is formed to operably receive one of a 2.4 GHz radio frequency signal or a 5.0 GHz radio frequency transceiver signal in a manner that minimizes duplication of circuitry and creates a combined circuit path for RF front end input stages for much of the input stage. More specifically, the embodiments of the present invention include separate amplification and mixing stages whose outputs are combined by a stabilized load with circuitry for removing a common mode feedback signal. As such, downstream components, such as amplifiers, filters, analog-to-digital converters, and other input path circuit elements, are not duplicated and may be used regardless of whether the dual-band transceiver is operating in a first or second frequency band. Operation is, in the described embodiment, only one frequency input at a time though the invention is not limited to such operation. More specifically, a first input section is operably coupled to receive a first local oscillation input and a first frequency band signal input. A second input section is coupled to receive a second local oscillation input and a second frequency band signal input. Outputs of the first and second input sections are produced to a stabilized load with a common mode feedback block for removing a common mode feedback signal. As such, an output signal is produced having a regulated DC level and having any common mode feedback signal eliminated there from.

Abstract translation: 双波段输入收发器模块被形成为以最小化电路复制的方式可操作地接收2.4GHz射频信号或5.0GHz射频收发器信号中的一个，并为RF前端输入级创建多个组合电路路径 的输入级。 更具体地，本发明的实施例包括单独的放大和混合级，其输出通过稳定的负载与用于去除共模反馈信号的电路组合。 因此，诸如放大器，滤波器，模数转换器和其它输入路径电路元件的下游部件不被复制，并且可以被使用，而不管双频带收发器是工作在第一或第二频带 。 在所描述的实施例中，操作是一次只输入一个频率，尽管本发明不限于此。 更具体地，第一输入部分可操作地耦合以接收第一本地振荡输入和第一频带信号输入。 第二输入部分被耦合以接收第二本地振荡输入和第二频带信号输入。 第一和第二输入部分的输出通过用于去除共模反馈信号的共模反馈块产生到稳定的负载。 因此，产生具有调节的DC电平并且从那里消除任何共模反馈信号的输出信号。

公开(公告)号：US20060003719A1

公开(公告)日：2006-01-05

申请号：US11183446

申请日：2005-07-18

Applicant: Hooman Darabi

Inventor： Hooman Darabi

IPC: H04B1/06 ,  H04B7/00 ,  H04L25/06

CPC classification number: H04W52/028 ,  Y02D70/122 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/22

Abstract: A bias filtering module with at least two capacitive levels satisfies both a settle time requirement and a filtering requirement using a voltage dependent filter module whose capacitance is a function of a voltage potential on the filtering circuitry output terminal. The final capacitance level is approximately three times larger than the initial capacitance level. MOS capacitors having a voltage dependent charge capacity within the bias filtering module are coupled between a plurality of bias lines and circuit common. In an alternate embodiment, a selectable first group of capacitors are switched into connection within the bias filtering module as a second group of capacitors approximately reach a fully charged state within a specified settle time to provide improved filtering.

Abstract translation: 具有至少两个电容电平的偏置滤波模块满足稳定时间要求和使用电压依赖滤波器模块的滤波要求，其电容是滤波电路输出端上的电压电位的函数。 最终电容电平大约是初始电容电平的三倍。 偏置滤波模块内具有与电压无关的电荷容量的MOS电容器耦合在多个偏置线和电路之间。 在替代实施例中，随着第二组电容器在指定的结算时间内大致达到完全充电状态，可选择的第一组电容器被切换成偏置滤波模块内的连接，以提供改进的滤波。