公开(公告)号：US20120285484A1

公开(公告)日：2012-11-15

申请号：US13106869

申请日：2011-05-13

申请人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B08B1/00

CPC分类号： H01L21/02052 ,  B08B1/00 ,  H01L21/67046

摘要： A wafer cleaning method includes: (1) providing a wafer cleaning apparatus comprising a sponge for scrubbing a surface of a semiconductor wafer to be cleaned; (2) implementing a pre-conditioning flow to pre-condition the sponge using a dummy wafer; and (3) performing a regular cleaning flow to scrub the surface of the semiconductor wafer to be cleaned using the pre-conditioned sponge. The dummy wafer has a plurality of upward protruding features on a surface of the dummy wafer for removing residual fibers or unwanted substances from the sponge.

摘要翻译： 晶片清洗方法包括：（1）提供一种晶片清洗装置，其包括用于擦洗要清洗的半导体晶片的表面的海绵; （2）实施预调节流程，以使用虚拟晶片对海绵进行预处理; 和（3）执行常规清洁流程以使用预先调节的海绵擦洗待清洁的半导体晶片的表面。 虚拟晶片在虚拟晶片的表面上具有多个向上突出的特征，用于从海绵中除去残留的纤维或不需要的物质。

公开(公告)号：US20120284936A1

公开(公告)日：2012-11-15

申请号：US13104964

申请日：2011-05-10

申请人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B08B1/04

CPC分类号： H01L21/67051 ,  H01L21/02052 ,  H01L21/67046

摘要： A post-CMP wafer cleaning apparatus includes a chamber; a plurality of rollers adapted to hold and rotate a wafer within the chamber; at least one brush adapted to scrub a surface of the wafer to be cleaned; and a liquid spraying device adapted to spray a liquid on the wafer, the liquid spraying device comprising two spray bars jointed together via a joint member.

摘要翻译： CMP后晶片清洗装置包括：腔室; 多个辊子，适于在所述腔室内保持和旋转晶片; 至少一个刷子，适于擦拭要清洁的晶片的表面; 以及适于将液体喷射在晶片上的液体喷射装置，所述液体喷射装置包括通过接头构件连接在一起的两个喷射杆。

公开(公告)号：US20120273874A1

公开(公告)日：2012-11-01

申请号：US13094796

申请日：2011-04-26

申请人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Tieh-Chiang Wu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66666 ,  H01L21/2257 ,  H01L27/10876 ,  H01L27/10885 ,  H01L29/7827

摘要： A method of forming a buried bit line is provided. A substrate is provided and a line-shaped trench region is defined in the substrate. A line-shaped trench is formed in the line-shaped trench region of the substrate. The line-shaped trench includes a sidewall surface and a bottom surface. Then, the bottom surface of the line-shaped trench is widened to form a curved bottom surface. Next, a doping area is formed in the substrate adjacent to the curved bottom surface. Lastly, a buried conductive layer is formed on the doping area such that the doping area and the buried conductive layer together constitute the buried bit line.

摘要翻译： 提供一种形成掩埋位线的方法。 提供衬底并且在衬底中限定线状沟槽区域。 在基板的线状沟槽区域中形成线状沟槽。 线状沟槽包括侧壁表面和底部表面。 然后，将线状沟槽的底面加宽，形成弯曲的底面。 接下来，在与该弯曲底面相邻的基板上形成掺杂区域。 最后，在掺杂区域上形成掩埋导电层，使得掺杂区域和掩埋导电层一起构成掩埋位线。

公开(公告)号：US20120267727A1

公开(公告)日：2012-10-25

申请号：US13093742

申请日：2011-04-25

申请人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L29/78 ,  H01L21/283

CPC分类号： H01L23/485 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit with a self-aligned contact includes a substrate with a transistor formed thereover, a dielectric spacer, a protection barrier, and a conductive layer. The transistor includes a mask layer and a pair of insulating spacers formed on opposite sides of the mask layer. The dielectric spacer partially covers at least one of the insulating spacers of the transistor. The protection barrier is formed over the dielectric spacer. The conductive layer is formed over the mask layer, the protection barrier, the dielectric spacer, the insulating spacer and the dielectric spacer as a self-aligned contact for contacting a source/drain region of the transistor.

摘要翻译： 具有自对准接触的集成电路包括其上形成有晶体管的衬底，介电间隔物，保护屏障和导电层。 晶体管包括掩模层和形成在掩模层的相对侧上的一对绝缘间隔物。 电介质间隔物部分地覆盖晶体管的至少一个绝缘间隔物。 保护屏障形成在电介质间隔物上。 导电层形成在掩模层，保护屏障，电介质间隔物，绝缘间隔物和介电间隔物上，作为用于接触晶体管的源/漏区的自对准接触。

公开(公告)号：US08178418B1

公开(公告)日：2012-05-15

申请号：US13093726

申请日：2011-04-25

申请人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Jar-Ming Ho ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/3086

摘要： A method for fabricating intra-device isolation structure is provided, including providing a semiconductor substrate with a mask layer formed thereover. A plurality of first trenches is formed in the semiconductor substrate and the mask layer. A first insulating layer is formed in the first trenches. The mask layer is partially removed to expose a portion of the first insulating layer in the first trenches. A protection spacer is formed on a sidewall surface of the portion of the first insulating layer exposed by the mask layer to partially expose a portion of the mask layer between the first insulating layer. An etching process is performed to the mask layer exposed by the protection spacer and the semiconductor substrate thereunder, and a plurality of second trenches is formed in the semiconductor substrate and the mask layer. A second insulating layer is formed in the second trenches. The protection spacer, the mask layer, the first insulating layer and the second insulating layer over a top surface of the semiconductor substrate are then removed.

摘要翻译： 提供一种用于制造器件间隔离结构的方法，包括提供其上形成有掩模层的半导体衬底。 在半导体衬底和掩模层中形成多个第一沟槽。 在第一沟槽中形成第一绝缘层。 部分去除掩模层以暴露第一沟槽中的第一绝缘层的一部分。 在由掩模层暴露的第一绝缘层的部分的侧壁表面上形成保护间隔物，以部分地暴露第一绝缘层之间的掩模层的一部分。 对由保护间隔物和其下的半导体衬底暴露的掩模层进行蚀刻处理，并且在半导体衬底和掩模层中形成多个第二沟槽。 在第二沟槽中形成第二绝缘层。 然后去除半导体衬底的顶表面上的保护间隔物，掩模层，第一绝缘层和第二绝缘层。

公开(公告)号：US06727159B2

公开(公告)日：2004-04-27

申请号：US10163239

申请日：2002-06-04

申请人： Yi-Nan Chen ,  Hsien-Wen Liu ,  Kaan-Lu Tzou

发明人： Yi-Nan Chen ,  Hsien-Wen Liu ,  Kaan-Lu Tzou

IPC分类号： H01L2176

CPC分类号： H01L21/02164 ,  H01L21/02274 ,  H01L21/02304 ,  H01L21/31612 ,  H01L21/76224

摘要： A method of forming a shallow trench isolation in a semiconductor substrate. First, a hard mask consisting of a pad nitride and a pad oxide is formed on the semiconductor substrate. The semiconductor substrate is anisotrpically etched to form a trench while the hard mask is used as the etching mask. A thermal oxide film is grown on the trench. Then, a nitride liner is formed on the thermal oxide film. Next, a silicon rich oxide layer is conformally deposited on the nitride liner by high density plasma chemical vapor deposition without a bias voltage applied to the semiconductor substrate. Then, a silicon oxide is deposited to fill the trench by high density plasma chemical vapor deposition while a bias voltage is applied to the semiconductor substrate.

摘要翻译： 一种在半导体衬底中形成浅沟槽隔离的方法。 首先，在半导体基板上形成由衬垫氮化物和衬垫氧化物构成的硬掩模。 在使用硬掩模作为蚀刻掩模的情况下，各向异性蚀刻半导体衬底以形成沟槽。 在沟槽上生长热氧化膜。 然后，在热氧化膜上形成氮化物衬垫。 接下来，通过高密度等离子体化学气相沉积在氮化物衬垫上共形沉积富硅氧化物层，而不施加施加到半导体衬底的偏置电压。 然后，沉积氧化硅以通过高密度等离子体化学气相沉积来填充沟槽，同时向半导体衬底施加偏置电压。

公开(公告)号：US08975137B2

公开(公告)日：2015-03-10

申请号：US13179581

申请日：2011-07-11

申请人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Wen-Chieh Wang ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/336 ,  H01L21/3205 ,  H01L21/461 ,  H01L21/3065 ,  H01L21/308

CPC分类号： H01L21/3065 ,  H01L21/3085

摘要： A process of forming a slit in a substrate is provided. A mask layer is formed on a substrate, wherein the mask layer does not include carbon. An etching process is performed to be substrate by using the mask layer as a mask, so as to form a slit in the substrate. The etching gas includes Cl2, CF4 and CHF3, a molar ratio of CF4 to CHF3 is about 0.5-0.8, and a molar ratio of F to Cl is about 0.4-0.8, for example. Further, the step of performing the etching process simultaneously removes the mask layer.

摘要翻译： 提供了在基板中形成狭缝的工艺。 在基板上形成掩模层，其中掩模层不包括碳。 通过使用掩模层作为掩模，进行蚀刻处理，以便在衬底中形成狭缝。 蚀刻气体包括Cl 2，CF 4和CHF 3，CF 4与CHF 3的摩尔比为约0.5-0.8，F与Cl的摩尔比例如约为0.4-0.8。 此外，进行蚀刻处理的步骤同时去除掩模层。

公开(公告)号：US08772119B2

公开(公告)日：2014-07-08

申请号：US13236656

申请日：2011-09-20

申请人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Kuo-Hui Su ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： H01L21/336

CPC分类号： H01L29/66606 ,  H01L21/28044 ,  H01L29/66553 ,  H01L29/78

摘要： A fabricating method of a transistor is provided. A patterned sacrificed layer is formed on a substrate, wherein the patterned sacrificed layer includes a plurality of openings exposing the substrate. By using the patterned sacrificed layer as a mask, a doping process is performed on the substrate, thereby forming a doped source region and a doped drain region in the substrate exposed by the openings. A selective growth process is performed to form a source and a drain on the doped source region and the doped drain region, respectively. The patterned sacrificed layer is removed to expose the substrate between the source and the drain. A gate is formed on the substrate between the source and the drain.

摘要翻译： 提供晶体管的制造方法。 图案化的牺牲层形成在衬底上，其中图案化牺牲层包括暴露衬底的多个开口。 通过使用图案化牺牲层作为掩模，在衬底上进行掺杂工艺，从而在由开口暴露的衬底中形成掺杂源极区域和掺杂漏极区域。 执行选择性生长工艺以在掺杂源极区域和掺杂漏极区域上分别形成源极和漏极。 去除图案化牺牲层以暴露源极和漏极之间的衬底。 在源极和漏极之间的衬底上形成栅极。

公开(公告)号：US08739806B2

公开(公告)日：2014-06-03

申请号：US13105874

申请日：2011-05-11

申请人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B08B3/04

CPC分类号： H01L21/67219 ,  B24B37/107 ,  B24B57/02 ,  H01L21/02052 ,  H01L21/67046

摘要： A chemical mechanical polishing (CMP) system includes a wafer polishing unit comprising a waste liquid sink for receiving a used slurry and a waste slurry drain piping for draining the used slurry; and a post-CMP cleaning unit coupled to the wafer polishing unit such that a used base chemical such as tetramethyl ammonium hydroxide (TMAH) produced from the post-CMP cleaning unit flows toward the wafer polishing unit to frequently wash at least the waste slurry drain piping in a real time fashion on a wafer by wafer basis.

摘要翻译： 化学机械抛光（CMP）系统包括晶片抛光单元，其包括用于接收使用过的浆料的废液槽和用于排出所用浆料的废浆排放管道; 以及与CMP晶片抛光单元联接的后CMP清洁单元，使得由CMP后清洁单元生产的诸如四甲基氢氧化铵（TMAH）的使用的基础化学品流向晶片抛光单元，以至少频繁地洗涤废料排水 以晶圆为基础，以实时的方式在晶圆上进行配管。

公开(公告)号：US08662963B2

公开(公告)日：2014-03-04

申请号：US13106822

申请日：2011-05-12

申请人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

发明人： Li-Chung Liu ,  Yi-Nan Chen ,  Hsien-Wen Liu

IPC分类号： B24B55/00

CPC分类号： H01L21/02057 ,  B24B37/34 ,  B24B57/02 ,  H01L21/67046

摘要： A chemical mechanical polishing (CMP) system includes a wafer polishing unit producing a used slurry; a slurry treatment system for receiving and treating the used slurry to thereby produce an extracted basic solution; and a post-CMP cleaning unit utilizing the extracted basic solution to wash a polished wafer surface. The post-CMP cleaning unit includes a plurality of rollers for supporting and rotating a wafer, a brush for scrubbing the wafer, and a spray bar disposed in proximity to the brush for spraying the extracted basic solution onto the polished wafer surface.

摘要翻译： 化学机械抛光（CMP）系统包括生产所用浆料的晶片抛光单元; 用于接收和处理所使用的浆料从而产生提取的碱性溶液的浆料处理系统; 以及利用所提取的碱性溶液洗涤抛光的晶片表面的后CMP清洁单元。 后CMP清洁单元包括用于支撑和旋转晶片的多个辊，用于洗涤晶片的刷子和布置在刷子附近的喷杆，用于将提取的碱性溶液喷射到抛光的晶片表面上。