公开(公告)号：US20210193519A1

公开(公告)日：2021-06-24

申请号：US16721243

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Feras Eid ,  Johanna M. Swan ,  Shawna M. Liff

IPC: H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.

公开(公告)号：US20210193518A1

公开(公告)日：2021-06-24

申请号：US16721235

申请日：2019-12-19

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Johanna M. Swan

IPC: H01L21/768 ,  H01L23/00

Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.

公开(公告)号：US10998272B2

公开(公告)日：2021-05-04

申请号：US16573943

申请日：2019-09-17

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Henning Braunisch ,  Shawna Liff ,  Brandon Rawlings ,  Veronica Strong ,  Johanna Swan

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: An electronic interposer may be formed using organic material layers, while allowing for the fabrication of high density interconnects within the electronic interposer without the use of embedded silicon bridges. This is achieved by forming the electronic interposer in three sections, i.e. an upper section, a lower section and a middle section. The middle section may be formed between the upper section and the lower section, wherein a thickness of each layer of the middle section is thinner than a thickness of any of the layers of the upper section and the lower section, and wherein conductive routes within the middle section have a higher density than conductive routes within the upper section and the lower section.

公开(公告)号：US20210125931A1

公开(公告)日：2021-04-29

申请号：US16667698

申请日：2019-10-29

Applicant: Intel Corporation

Inventor： Georgios Dogiamis ,  Aleksandar Aleksov ,  Feras Eid ,  Telesphor Kamgaing ,  Johanna M. Swan

IPC: H01L23/538 ,  B81B7/00 ,  H01L23/28 ,  H01L23/552 ,  H01L21/56

Abstract: Embodiments may relate to a microelectronic package that includes a substrate with an overmold material. The microelectronic package may include a die in the overmold material, and an inactive side of the die may be coupled with a face of the substrate. A through-mold via (TMV) may be present in the overmold material. The TMV may be communicatively coupled with the substrate, and an active side of the die may be communicatively coupled with the TMV by a trace in the overmold material. Other embodiments may be described or claimed.

公开(公告)号：US10971416B2

公开(公告)日：2021-04-06

申请号：US16526497

申请日：2019-07-30

Applicant: Intel Corporation

Inventor： Krishna Bharath ,  Mathew J. Manusharow ,  Adel A. Elsherbini ,  Mihir K. Roy ,  Aleksandar Aleksov ,  Yidnekachew S. Mekonnen ,  Javier Soto Gonzalez ,  Feras Eid ,  Suddhasattwa Nad ,  Meizi Jiao

IPC: H01L23/52 ,  H01L23/12 ,  H01L23/48 ,  H01L21/48 ,  H01L23/498

Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.

公开(公告)号：US10950919B2

公开(公告)日：2021-03-16

申请号：US16325522

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios C. Dogiamis ,  Sasha N. Oster ,  Adel A. Elsherbini ,  Brandon M. Rawlings ,  Aleksandar Aleksov ,  Shawna M. Liff ,  Richard J. Dischler ,  Johanna M. Swan

IPC: H01P5/02 ,  H01P3/12 ,  H01P3/16 ,  H01P1/04 ,  H01P1/02 ,  H01P11/00

Abstract: An apparatus comprises a waveguide section including an outer layer of conductive material tubular in shape and having multiple ends; and a joining feature on at least one of the ends of the waveguide section configured for joining to a second separate waveguide section.

公开(公告)号：US20210067132A1

公开(公告)日：2021-03-04

申请号：US16550673

申请日：2019-08-26

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Georgios Dogiamis ,  Feras Eid ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H03H9/08 ,  H01L27/20 ,  H03H9/70 ,  H01L23/552 ,  H01L23/367 ,  H01L25/16 ,  H01L23/498 ,  H03H3/02 ,  H03H9/54 ,  H03H9/05 ,  H01L23/66

Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM). The RF FEM may include an integrated die with an active portion and an acoustic wave resonator (AWR) portion adjacent to the active portion. The RF FEM may further include a lid coupled with the die. The lid may at least partially overlap the AWR portion at a surface of the die. Other embodiments may be described or claimed.

公开(公告)号：US20210043543A1

公开(公告)日：2021-02-11

申请号：US16533065

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: H01L23/427 ,  H01L23/00 ,  H03H9/46 ,  H01L23/48 ,  H01L23/66 ,  H01L23/31 ,  H01L23/373 ,  H01L23/38

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

公开(公告)号：US20210041182A1

公开(公告)日：2021-02-11

申请号：US16533235

申请日：2019-08-06

Applicant: Intel Corporation

Inventor： Feras Eid ,  Telesphor Kamgaing ,  Georgios Dogiamis ,  Aleksandar Aleksov ,  Johanna M. Swan

IPC: F28D15/04 ,  H01L23/367 ,  H01L23/38 ,  H01L23/427

Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.

公开(公告)号：US20200303329A1

公开(公告)日：2020-09-24

申请号：US16397718

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Henning Braunisch ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov

IPC: H01L23/66 ,  H01L23/00

Abstract: Embodiments may relate to a microelectronic package that includes a radio frequency (RF) chip coupled with a die by interconnects with a first pitch. The RF chip may further be coupled with a waveguide of a package substrate by interconnects with a second pitch that is different than the first pitch. The RF chip may facilitate conveyance of data to the waveguide as an electromagnetic signal with a frequency greater than approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.