公开(公告)号：US09467279B2

公开(公告)日：2016-10-11

申请号：US14498633

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Sean M. Gulley ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  G09C1/00 ,  H04L9/08

CPC classification number: H04L9/0869 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/3895 ,  G06F21/72 ,  G09C1/00 ,  H04L9/0618 ,  H04L2209/12 ,  H04L2209/24

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

Abstract translation: 指令和逻辑提供单指令多数据（SIMD）SM4圆切片操作。 指令的实施例指定第一和第二源数据操作数集合，以及替换功能指示符，例如， 在一个立即操作数。 处理器的实施例可以包括响应于第一指令的加密单元，以在第一源数据操作数集合的一部分上执行与来自第二源数据操作数集合的对应密钥的一组SM4-圆交换，以响应于 替代功能指示符，其指示第一替换功能，响应于指示第二替代函数的替代函数指示符，使用来自第二源数据操作数集合的相应常数的第一源数据操作数集合的另一部分来执行SM4密钥生成片段 并将第一指令的一组结果元素存储在SIMD目的地寄存器中。

公开(公告)号：US09419648B1

公开(公告)日：2016-08-16

申请号：US14858752

申请日：2015-09-18

Applicant: Intel Corporation

Inventor： James D. Guilford ,  Vinodh Gopal ,  Gilbert M. Wolrich ,  Daniel F. Cutter

IPC: H03M7/40 ,  G06F3/06

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0653 ,  G06F3/0673 ,  G06F8/52 ,  G06F12/1018 ,  G06F12/1027 ,  G06F2212/401 ,  G06F2212/68 ,  H03M7/3086 ,  H03M7/40

Abstract: In one embodiment, a processing system is provided. The processing system includes a memory for storing an input bit stream and a processing logic coupled to the memory. The processing logic to identify, within the input bit stream, a first bit subsequence of an input bit sequence and a second bit subsequence of the input bit sequence. A first score reflecting the length of the first bit subsequence and the distance between the input bit sequence and the first bit subsequence and a second score reflecting the length of the second bit subsequence, within the input bit stream, and the distance between the input bit sequence and the second bit subsequence is determined. In view of the first score and the second score, one of the first bit subsequence or the second bit subsequence is selected. A code representing a selected bit subsequence is appended to an output bit sequence.

Abstract translation: 在一个实施例中，提供了处理系统。 处理系统包括用于存储输入比特流的存储器和耦合到存储器的处理逻辑。 该处理逻辑在输入比特流内识别输入比特序列的第一比特子序列和输入比特序列的第二比特子序列。 反映第一比特子序列的长度和输入比特序列与第一比特子序列之间的距离的第一分数和反映输入比特流内的第二比特子序列的长度的第二分数以及输入比特序列之间的距离 序列和第二位子序列被确定。 考虑到第一分数和第二分数，选择第一比特子序列或第二比特子序列之一。 表示所选位子序列的代码被附加到输出比特序列。

公开(公告)号：US20160094340A1

公开(公告)日：2016-03-31

申请号：US14498633

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Gilbert M. Wolrich ,  Sean M. Gulley ,  Vinodh Gopal ,  Kirk S. Yap ,  Wajdi K. Feghali

IPC: H04L9/06 ,  G06F21/72 ,  G06F9/30 ,  H04L9/08

CPC classification number: H04L9/0869 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/3877 ,  G06F9/3887 ,  G06F9/3895 ,  G06F21/72 ,  G09C1/00 ,  H04L9/0618 ,  H04L2209/12 ,  H04L2209/24

Abstract: Instructions and logic provide for a Single Instruction Multiple Data (SIMD) SM4 round slice operation. Embodiments of an instruction specify a first and a second source data operand set, and substitution function indicators, e.g. in an immediate operand. Embodiments of a processor may include encryption units, responsive to the first instruction, to: perform a slice of SM4-round exchanges on a portion of the first source data operand set with a corresponding keys from the second source data operand set in response to a substitution function indicator that indicates a first substitution function, perform a slice of SM4 key generations using another portion of the first source data operand set with corresponding constants from the second source data operand set in response to a substitution function indicator that indicates a second substitution function, and store a set of result elements of the first instruction in a SIMD destination register.

Abstract translation: 指令和逻辑提供单指令多数据（SIMD）SM4圆切片操作。 指令的实施例指定第一和第二源数据操作数集合，以及替换功能指示符，例如， 在一个立即操作数。 处理器的实施例可以包括响应于第一指令的加密单元，以在第一源数据操作数集合的一部分上执行与来自第二源数据操作数集合的对应密钥的一组SM4-圆交换，以响应于 替代功能指示符，其指示第一替换功能，响应于指示第二替代函数的替代函数指示符，使用来自第二源数据操作数集合的相应常数的第一源数据操作数集合的另一部分来执行SM4密钥生成片段 并将第一指令的一组结果元素存储在SIMD目的地寄存器中。

公开(公告)号：US09164762B2

公开(公告)日：2015-10-20

申请号：US13947958

申请日：2013-07-22

Applicant: INTEL CORPORATION

Inventor： Vinodh Gopal ,  James D. Gulilford ,  Gilbert M. Wolrich ,  Waidi K. Feghali ,  Erdinc Ozturk ,  Martin G. Dixon ,  Sean P. Mirkes ,  Bret L. Toll ,  Maxim Loktyukhin ,  Mark C. Davis ,  Alexandre J. Farcy

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30094 ,  G06F9/30098

Abstract: A method of one aspect may include receiving a rotate instruction. The rotate instruction may indicate a source operand and a rotate amount. A result may be stored in a destination operand indicated by the rotate instruction. The result may have the source operand rotated by the rotate amount. Execution of the rotate instruction may complete without reading a carry flag.

Abstract translation: 一个方面的方法可以包括接收旋转指令。 旋转指令可以指示源操作数和旋转量。 结果可以存储在由旋转指令指示的目标操作数中。 结果可能使源操作数旋转了旋转量。 旋转指令的执行可以在不读取进位标志的情况下完成。

公开(公告)号：US20140205084A1

公开(公告)日：2014-07-24

申请号：US13995457

申请日：2011-12-22

Applicant: INTEL CORPORATION

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  Vinodh Gopal ,  James D. Guilford ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC: H04L9/14 ,  G06F21/60

CPC classification number: H04L9/14 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3893 ,  G06F21/602 ,  H04L9/3239

Abstract: A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.

Abstract translation: 描述了一种方法。 该方法包括执行一个或多个JH_SBOX_L指令以在JH状态上执行S-Box映射和线性（L）变换，并且一旦S-Box映射和 L变换。

公开(公告)号：US20140164467A1

公开(公告)日：2014-06-12

申请号：US13996529

申请日：2011-12-23

Applicant: INTEL CORPORATION

Inventor： Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Vinodh Gopal ,  Wajdi K. Feghali ,  Sean M. Gulley ,  Martin G. Dixon

IPC: G06F7/57

CPC classification number: G06F9/3016 ,  G06F7/525 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3893

Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

Abstract translation: 描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数和第二输入操作数相乘并且呈现下一部分的第一指令 其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。