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公开(公告)号：US08361847B2
公开(公告)日：2013-01-29
申请号：US13009029
申请日：2011-01-19
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： A method for forming a stressed channel field effect transistor (FET) with source/drain buffers includes etching cavities in a substrate on either side of a gate stack located on the substrate; depositing source/drain buffer material in the cavities; etching the source/drain buffer material to form vertical source/drain buffers adjacent to a channel region of the FET; and depositing source/drain stressor material in the cavities adjacent to and over the vertical source/drain buffers.
摘要翻译： 用于形成具有源极/漏极缓冲器的应力通道场效应晶体管（FET）的方法包括在位于衬底上的栅极堆叠的任一侧上的衬底中的蚀刻腔; 在空腔中沉积源极/漏极缓冲材料; 蚀刻源极/漏极缓冲材料以形成与FET的沟道区相邻的垂直源极/漏极缓冲器; 以及将源极/漏极应力源材料沉积在与垂直源极/漏极缓冲器相邻并在其上方的空腔中。
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102.发明授权Method to optimize work function in complementary metal oxide semiconductor (CMOS) structures 有权在互补金属氧化物半导体（CMOS）结构中优化功函数的方法公开(公告)号：US08354313B2
公开(公告)日：2013-01-15
申请号：US12770792
申请日：2010-04-30
IPC分类号： H01L21/8236 , H01L21/8234 , H01L21/4763
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/823807 , H01L21/823842 , H01L29/1054 , H01L29/42372 , H01L29/665 , H01L29/6656 , H01L29/7843
摘要： In one embodiment, the method for forming a complementary metal oxide semiconductor (CMOS) device includes providing a semiconductor substrate including a first device region and a second device region. An n-type conductivity semiconductor device is formed in one of the first device region or the second device region using a gate structure first process, in which the n-type conductivity semiconductor device includes a gate structure having an n-type work function metal layer. A p-type conductivity semiconductor device is formed in the other of the first device region or the second device region using a gate structure last process, in which the p-type conductivity semiconductor device includes a gate structure including a p-type work function metal layer.
摘要翻译： 在一个实施例中，形成互补金属氧化物半导体（CMOS）器件的方法包括提供包括第一器件区域和第二器件区域的半导体衬底。 使用栅极结构第一工艺在第一器件区域或第二器件区域之一中形成n型导电性半导体器件，其中n型导电性半导体器件包括具有n型功函数金属层的栅极结构 。 使用栅极结构最后工艺在第一器件区域或第二器件区域中的另一个中形成p型导电性半导体器件，其中p型导电半导体器件包括具有p型功函数金属 层。
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103.发明申请WIRING SWITCH DESIGNS BASED ON A FIELD EFFECT DEVICE FOR RECONFIGURABLE INTERCONNECT PATHS 有权基于可重构互连网络的场效应设备的接线开关设计公开(公告)号：US20120306017A1
公开(公告)日：2012-12-06
申请号：US13479946
申请日：2012-05-24
CPC分类号： H01L23/525 , H01L27/124 , H01L2924/0002 , H03K19/1736 , H01L2924/00
摘要： An integrated circuit, including a substrate, at least one metal wiring layer disposed above the substrate. The metal wiring layer including a wiring switch and a plurality of patterned conductors. The wiring switch including a back gate field effect transistor (BGFET).
摘要翻译： 一种集成电路，包括基板，设置在基板上方的至少一个金属布线层。 金属布线层包括布线开关和多个图案化导体。 布线开关包括背栅场效应晶体管（BGFET）。
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公开(公告)号：US20120286371A1
公开(公告)日：2012-11-15
申请号：US13558664
申请日：2012-07-26
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L29/66537 , H01L29/66575 , H01L29/7833
摘要： A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, wherein the channel region includes a source transition portion including n-type and p-type ions and a drain transition portion including n-type and p-type ions, and a gate stack portion disposed on the channel region.
摘要翻译： 场效应晶体管器件包括：衬底，其包括源区域，漏极区域和设置在源极区域和漏极区域之间的沟道区域，其中源极区域与源极延伸部分连接到沟道区域，并且漏极 区域与漏极延伸部分连接到沟道区域，其中沟道区域包括包括n型和p型离子的源极过渡部分和包括n型和p型离子的漏极过渡部分，以及栅极堆叠 部分设置在通道区域上。
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105.发明申请公开(公告)号：US20120286360A1
公开(公告)日：2012-11-15
申请号：US13556608
申请日：2012-07-24
IPC分类号： H01L29/78
CPC分类号： H01L29/66545 , H01L29/66553 , H01L29/66606 , H01L29/7834
摘要： A field effect transistor device includes a substrate including a source region, a drain region, and a channel region disposed between the source region and the drain region, wherein the source region is connected to the channel region with a source extension portion, and the drain region is connected to the channel region with a drain extension portion, a first spacer portion disposed on the source region, the drain region and a first portion of the source extension portion, and a first portion of the drain extension portion, a second spacer portion disposed on a second portion of the source extension portion, and a second portion of the drain extension portion, a gate stack portion disposed on the channel region.
摘要翻译： 场效应晶体管器件包括：衬底，其包括源区域，漏极区域和设置在源极区域和漏极区域之间的沟道区域，其中源极区域与源极延伸部分连接到沟道区域，并且漏极 区域连接到具有漏极延伸部分的沟道区域，设置在源极区域上的第一间隔部分，漏极区域和源极延伸部分的第一部分以及漏极延伸部分的第一部分，第二间隔部分 设置在源极延伸部分的第二部分上，以及漏极延伸部分的第二部分，设置在沟道区域上的栅极叠层部分。
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公开(公告)号：US07704830B2
公开(公告)日：2010-04-27
申请号：US11759518
申请日：2007-06-07
IPC分类号： H01L21/336
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/42328 , H01L29/7881
摘要： A self-aligned split gate bitcell includes first and second regions of charge storage material separated by a gap devoid of charge storage material. Spacers are formed along sidewalls of sacrificial layer extending above and on opposite sides of the bitcell stack, wherein the spacers are separated from one another by at least a gap length. Etching the bitcell stack, selective to the spacers, forms a gap that splits the bitcell stack into first and second gates which together form the split gate bitcell stack. A storage portion of bitcell stack is also etched, wherein etching extends the gap and separates the corresponding layer into first and second separate regions, the extended gap being devoid of charge storage material. Dielectric material is deposited over the gap and etched back to expose a top surface of the sacrificial layer, which is thereafter removed to expose sidewalls of the split gate bitcell stack.
摘要翻译： 自对准分离栅极位单元包括由没有电荷存储材料的间隙分开的电荷存储材料的第一和第二区域。 间隔物形成在牺牲层的侧壁上，该牺牲层在位单元堆叠的上方和相对侧上延伸，其中间隔物彼此间隔至少间隙长度。 刻蚀对间隔物有选择性的位单元堆叠形成了将位单元堆叠分成第一和第二栅极的间隙，这些栅极组共同构成了分离栅极位单元堆叠。 比特单元堆叠的存储部分也被蚀刻，其中蚀刻延伸间隙并将相应的层分离成第一和第二分离区域，扩展间隙没有电荷存储材料。 电介质材料沉积在间隙上并被回蚀以暴露牺牲层的顶表面，此牺牲层此后被去除以暴露分裂栅极位晶胞堆叠的侧壁。
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公开(公告)号：US07579238B2
公开(公告)日：2009-08-25
申请号：US11668210
申请日：2007-01-29
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/513 , H01L29/66772 , H01L29/7887
摘要： In making a multi-bit memory cell, a first insulating layer is formed over a semiconductor substrate. A second insulating layer is formed over the first insulating layer. A layer of gate material is formed over the second insulating layer and patterned to leave a gate portion. The second insulating layer is etched to undercut the gate portion and leave a portion of the second insulating layer between the first insulating layer and the gate portion. Nanocrystals are formed on the first insulating layer. A first portion of the nanocrystals is under the gate portion on a first side of the portion of the second insulating layer and a second portion of the nanocrystals is under the gate portion on a second side of the portion of the second insulating layer. The first and second portions of the nanocrystals are for storing logic states of first and second bits, respectively.
摘要翻译： 在制造多位存储单元时，在半导体衬底上形成第一绝缘层。 在第一绝缘层上形成第二绝缘层。 一层栅极材料形成在第二绝缘层之上并图案化以留下栅极部分。 蚀刻第二绝缘层以切割栅极部分，并将第二绝缘层的一部分留在第一绝缘层和栅极部分之间。 在第一绝缘层上形成纳米晶体。 纳米晶体的第一部分在第二绝缘层部分的第一侧上的栅极部分下方，并且纳米晶体的第二部分位于第二绝缘层部分的第二侧的栅极部分的下方。 纳米晶体的第一和第二部分分别用于存储第一和第二位的逻辑状态。
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108.发明授权公开(公告)号：US07563662B2
公开(公告)日：2009-07-21
申请号：US11084283
申请日：2005-03-18
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , B82Y10/00 , H01L27/105 , H01L27/11546
摘要： A process for forming an electronic device can be performed, such that as little as one gate electric layer may be formed within each region of the electronic device. In one embodiment, the electronic device can include an NVM array and other regions that have different gate dielectric layers. By protecting the field isolation regions within the NVM array and other regions while gate dielectric layer are formed, the field isolation regions may be exposed to as little as one oxide etch between the time any of the gate dielectric layers are formed the time such gate dielectric layers are covered by gate electrode layers. The process helps to reduce field isolation erosion and reduce problems associated therewith.
摘要翻译： 可以执行用于形成电子器件的工艺，使得可以在电子器件的每个区域内形成少至一个栅极电层。 在一个实施例中，电子设备可以包括NVM阵列和具有不同栅介电层的其它区域。 通过在形成栅介质层的同时保护NVM阵列和其它区域内的场隔离区域，在形成任何栅极电介质层的时间之间，场隔离区可能暴露于少至一个氧化物蚀刻， 层被栅极电极层覆盖。 该过程有助于减少场隔离侵蚀并减少与之相关的问题。
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公开(公告)号：US20090166712A1
公开(公告)日：2009-07-02
申请号：US12397849
申请日：2009-03-04
IPC分类号： H01L29/78
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译： 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。
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公开(公告)号：US20090085023A1
公开(公告)日：2009-04-02
申请号：US11864257
申请日：2007-09-28
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1273 , H01L45/144 , H01L45/148
摘要： A phase change memory cell has a first electrode, a heater, a phase change material, and a second electrode. The heater is over the first electrode, and the heater comprises a pillar. The phase change material is around the heater. The second electrode is electrically coupled to the phase change material. In some embodiments, a method includes forming a electrode layer over a substrate, depositing a first layer, providing nanoclusters over the first layer, and etching the first layer. The first layer comprises one of a group consisting of a heater material and a phase change material. The first layer may be etched using the nanocluster defined pattern to form pillars from the first layer.
摘要翻译： 相变存储单元具有第一电极，加热器，相变材料和第二电极。 加热器在第一电极之上，并且加热器包括支柱。 相变材料在加热器周围。 第二电极电耦合到相变材料。 在一些实施例中，一种方法包括在衬底上形成电极层，沉积第一层，在第一层上提供纳米团簇，以及蚀刻第一层。 第一层包括由加热器材料和相变材料组成的组中的一个。 可以使用纳米簇限定图案蚀刻第一层，以形成来自第一层的柱。
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