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公开(公告)号：US07800164B2
公开(公告)日：2010-09-21
申请号：US12397849
申请日：2009-03-04
IPC分类号： H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译： 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。
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公开(公告)号：US20080121966A1
公开(公告)日：2008-05-29
申请号：US11530053
申请日：2006-09-08
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译： 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。
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公开(公告)号：US07517747B2
公开(公告)日：2009-04-14
申请号：US11530053
申请日：2006-09-08
IPC分类号： H01L21/8238
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译： 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。
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公开(公告)号：US20080121967A1
公开(公告)日：2008-05-29
申请号：US11530054
申请日：2006-09-08
IPC分类号： H01L29/78 , H01L21/3205
CPC分类号： H01L29/42332 , B82Y10/00 , H01L29/40114 , H01L29/513 , H01L29/7881
摘要： A method of forming a semiconductor device, which is preferably a memory cell, includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, wherein each of the plurality of discrete storage elements has a diameter value that is approximately equal to each other, and forming a second dielectric layer over the plurality of discrete storage elements, wherein the second dielectric layer has a thickness, wherein the ratio of the thickness of the second dielectric to the diameter value is less than approximately 0.8. The spacing between the plurality of discrete storage elements may be greater than or equal to approximately the thickness of the second dielectric layer.
摘要翻译： 形成半导体器件的方法，其优选地是存储单元，包括在半导体衬底上形成第一介电层，在第一介电层上形成多个离散存储元件，其中多个离散存储元件中的每一个具有 并且在所述多个分立存储元件上形成第二电介质层，其中所述第二电介质层具有厚度，其中所述第二电介质的厚度与所述直径值的比值小于 约0.8。 多个离散存储元件之间的间隔可以大于或等于第二电介质层的厚度。
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公开(公告)号：US07160775B2
公开(公告)日：2007-01-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
发明人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译： 在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电 场到纳米团簇放电半导体器件。 施加紫外线（UV）光时可能会发生电场。 在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。
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公开(公告)号：US20090166712A1
公开(公告)日：2009-07-02
申请号：US12397849
申请日：2009-03-04
IPC分类号： H01L29/78
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译： 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。
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公开(公告)号：US20080164512A1
公开(公告)日：2008-07-10
申请号：US11620075
申请日：2007-01-05
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L21/84 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/1203 , H01L27/15 , H01L29/66825 , H01L29/788
摘要： A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.
摘要翻译： 半导体器件具有半导体衬底，其又具有顶部半导体层部分和顶部半导体层部分下方的主要支撑部分。 互连层在半导体层之上。 存储器阵列位于顶部半导体层部分和互连层的一部分中。 通过去除主要支撑部分的至少一部分并且在移除步骤之后，从与互连层相对的一侧将光施加到存储器阵列来擦除存储器。 结果是存储器阵列从背面接收光并被擦除。
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公开(公告)号：US06958265B2
公开(公告)日：2005-10-25
申请号：US10663621
申请日：2003-09-16
申请人： Robert F. Steimle , Ramachandran Muralidhar , Wayne M. Paulson , Rajesh A. Rao , Bruce E. White, Jr. , Erwin J. Prinz
发明人： Robert F. Steimle , Ramachandran Muralidhar , Wayne M. Paulson , Rajesh A. Rao , Bruce E. White, Jr. , Erwin J. Prinz
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/115 , H01L29/423
CPC分类号： B82Y10/00 , H01L21/28273 , H01L27/115 , H01L29/42332
摘要： A process of forming a device with nanoclusters. The process includes forming nanoclusters (e.g. silicon nanocrystals) and forming an oxidation barrier layer over the nanoclusters to inhibit oxidizing agents from oxidizing the nanoclusters during a subsequent formation of a dielectric of the device. At least a portion of the oxidation barrier layer is removed after the formation of the dielectric. In one example, the device is a memory wherein the nanoclusters are utilized as charge storage locations for charge storage transistors of the memory. In this example, the oxidation barrier layer protects the nanoclusters from oxidizing agents due to the formation of gate dielectric for high voltage transistors of the memory.
摘要翻译： 用纳米团簇形成装置的方法。 该方法包括形成纳米团簇（例如硅纳米晶体）并在纳米簇上形成氧化阻挡层，以在随后形成器件的电介质期间抑制氧化剂氧化纳米团簇。 在形成电介质后，去除至少一部分氧化阻挡层。 在一个示例中，该器件是其中纳米团簇用作存储器的电荷存储晶体管的电荷存储位置的存储器。 在该实施例中，氧化阻挡层由于形成用于存储器的高压晶体管的栅极电介质而保护纳米团簇免受氧化剂的影响。
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公开(公告)号：US07820491B2
公开(公告)日：2010-10-26
申请号：US11620075
申请日：2007-01-05
CPC分类号： H01L27/105 , H01L21/84 , H01L27/112 , H01L27/11206 , H01L27/11517 , H01L27/1203 , H01L27/15 , H01L29/66825 , H01L29/788
摘要： A semiconductor device has a semiconductor substrate that in turn has a top semiconductor layer portion and a major supporting portion under the top semiconductor layer portion. An interconnect layer is over the semiconductor layer. A memory array is in a portion of the top semiconductor layer portion and a portion of the interconnect layer. The memory is erased by removing at least a portion of the major supporting portion and, after the step of removing, applying light to the memory array from a side opposite the interconnect layer. The result is that the memory array receives light from the backside and is erased.
摘要翻译： 半导体器件具有半导体衬底，其又具有顶部半导体层部分和顶部半导体层部分下方的主要支撑部分。 互连层在半导体层之上。 存储器阵列位于顶部半导体层部分和互连层的一部分中。 通过去除主要支撑部分的至少一部分并且在移除步骤之后，从与互连层相对的一侧将光施加到存储器阵列来擦除存储器。 结果是存储器阵列从背面接收光并被擦除。
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公开(公告)号：US07361567B2
公开(公告)日：2008-04-22
申请号：US11043826
申请日：2005-01-26
IPC分类号： H01L21/331 , H01L21/20 , H01L21/8242 , H01L21/31 , H01L21/469
CPC分类号： H01L29/42348 , B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/513 , H01L29/518
摘要： A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.
摘要翻译： 纳米晶体非易失性存储器（NVM）在控制栅极和纳米晶体之间具有电介质，其具有足够的氮含量以减少电介质中的电子被俘获的位置。 这是通过对氮浓度进行分级而实现的。 靠近纳米晶体的氮浓度最高，其中电子/空穴阱的浓度趋于最高，并且朝向电子/空穴陷阱的浓度较低的对照栅极减小。 已经发现这具有减少电荷被捕获的位置数量的有益效果。
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